A digital signal processing circuit including: a multiplier circuit; a plurality of. multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit coupled to plurality of multiplexers and controlled by a second opcode. ...http://www.google.com.mx/patents/US20060190516?utm_source=gb-gplus-sharePatent US20060190516 - Digital signal processing element having an arithmetic logic unit
