DE69426355T2 - Umfangreiche Datenbusarchitektur - Google Patents
Umfangreiche DatenbusarchitekturInfo
- Publication number
- DE69426355T2 DE69426355T2 DE69426355T DE69426355T DE69426355T2 DE 69426355 T2 DE69426355 T2 DE 69426355T2 DE 69426355 T DE69426355 T DE 69426355T DE 69426355 T DE69426355 T DE 69426355T DE 69426355 T2 DE69426355 T2 DE 69426355T2
- Authority
- DE
- Germany
- Prior art keywords
- data bus
- bus architecture
- comprehensive data
- comprehensive
- architecture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/226,034 US5742544A (en) | 1994-04-11 | 1994-04-11 | Wide databus architecture |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69426355D1 DE69426355D1 (de) | 2001-01-04 |
DE69426355T2 true DE69426355T2 (de) | 2001-05-31 |
Family
ID=22847293
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69426355T Expired - Lifetime DE69426355T2 (de) | 1994-04-11 | 1994-09-28 | Umfangreiche Datenbusarchitektur |
Country Status (4)
Country | Link |
---|---|
US (11) | US5742544A (de) |
EP (1) | EP0676766B1 (de) |
JP (1) | JPH0836885A (de) |
DE (1) | DE69426355T2 (de) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5742544A (en) * | 1994-04-11 | 1998-04-21 | Mosaid Technologies Incorporated | Wide databus architecture |
KR100253565B1 (ko) * | 1997-04-25 | 2000-05-01 | 김영환 | 동기식 기억소자의 양방향 데이타 입출력 회로 및 그 제어방법 |
JP3933769B2 (ja) * | 1997-10-20 | 2007-06-20 | 富士通株式会社 | 半導体記憶装置 |
DE10021776C2 (de) * | 2000-05-04 | 2002-07-18 | Infineon Technologies Ag | Layout eines Sense-Verstärkers mit beschleunigter Signalauswertung |
US6240008B1 (en) * | 2000-06-09 | 2001-05-29 | Silicon Access Networks, Inc. | Read zero DRAM |
US6620723B1 (en) * | 2000-06-27 | 2003-09-16 | Applied Materials, Inc. | Formation of boride barrier layers using chemisorption techniques |
JP2004171742A (ja) * | 2002-11-08 | 2004-06-17 | Hitachi Ltd | 半導体装置 |
DE102005003461A1 (de) * | 2005-01-25 | 2006-08-03 | Infineon Technologies Ag | Integrierter Halbleiterspeicher und Verfahren zum Betreiben eines Halbleiterspeichers |
US7372092B2 (en) * | 2005-05-05 | 2008-05-13 | Micron Technology, Inc. | Memory cell, device, and system |
US7352649B2 (en) * | 2005-07-21 | 2008-04-01 | Micron Technology, Inc. | High speed array pipeline architecture |
US8506402B2 (en) * | 2009-06-01 | 2013-08-13 | Sony Computer Entertainment America Llc | Game execution environments |
US20110044121A1 (en) * | 2009-08-20 | 2011-02-24 | Kim Joung-Yeal | Semiconductor memory device having device for controlling bit line loading and improving sensing efficiency of bit line sense amplifier |
US8164942B2 (en) * | 2010-02-01 | 2012-04-24 | International Business Machines Corporation | High performance eDRAM sense amplifier |
WO2011106262A2 (en) | 2010-02-23 | 2011-09-01 | Rambus Inc. | Hierarchical memory architecture |
US8873314B2 (en) * | 2010-11-05 | 2014-10-28 | Micron Technology, Inc. | Circuits and methods for providing data to and from arrays of memory cells |
US20120151232A1 (en) * | 2010-12-12 | 2012-06-14 | Fish Iii Russell Hamilton | CPU in Memory Cache Architecture |
JP6105266B2 (ja) | 2011-12-15 | 2017-03-29 | 株式会社半導体エネルギー研究所 | 記憶装置 |
US8760911B2 (en) * | 2012-04-04 | 2014-06-24 | Matthew Christian | Memory system configured for use in a binary predictor |
JP6295863B2 (ja) | 2014-07-16 | 2018-03-20 | 富士通株式会社 | 電子部品、電子装置及び電子装置の製造方法 |
US20160088078A1 (en) * | 2014-09-18 | 2016-03-24 | Ningbo Sunny Opotach Co.,Ltd. | Instant Photo Sharing Arrangement and Method |
EP3934751A1 (de) | 2019-03-08 | 2022-01-12 | Mevion Medical Systems, Inc. | Kollimator und energieabbau für ein teilchentherapiesystem |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3387286A (en) * | 1967-07-14 | 1968-06-04 | Ibm | Field-effect transistor memory |
US4208730A (en) * | 1978-08-07 | 1980-06-17 | Rca Corporation | Precharge circuit for memory array |
US4558435A (en) * | 1983-05-31 | 1985-12-10 | Rca Corporation | Memory system |
JPS6148194A (ja) | 1984-08-15 | 1986-03-08 | Fujitsu Ltd | 半導体記憶装置 |
US4807194A (en) * | 1986-04-24 | 1989-02-21 | Matsushita Electric Industrial Co., Ltd. | Seimiconductor memory device having sub bit lines |
US4920517A (en) * | 1986-04-24 | 1990-04-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device having sub bit lines |
DE3628286A1 (de) | 1986-08-20 | 1988-02-25 | Staerk Juergen Dipl Ing Dipl I | Prozessor mit integriertem speicher |
JP2618938B2 (ja) * | 1987-11-25 | 1997-06-11 | 株式会社東芝 | 半導体記憶装置 |
JPH01241093A (ja) * | 1988-03-22 | 1989-09-26 | Fujitsu Ltd | 半導体記憶装置 |
JP2633645B2 (ja) * | 1988-09-13 | 1997-07-23 | 株式会社東芝 | 半導体メモリ装置 |
JP2865712B2 (ja) | 1989-07-12 | 1999-03-08 | 株式会社日立製作所 | 半導体記憶装置 |
JP2777247B2 (ja) * | 1990-01-16 | 1998-07-16 | 三菱電機株式会社 | 半導体記憶装置およびキャッシュシステム |
US5134616A (en) * | 1990-02-13 | 1992-07-28 | International Business Machines Corporation | Dynamic ram with on-chip ecc and optimized bit and word redundancy |
US5553032A (en) * | 1990-03-30 | 1996-09-03 | Fujitsu Limited | Dynamic random access memory wherein timing of completion of data reading is advanced |
JPH03283179A (ja) | 1990-03-30 | 1991-12-13 | Fujitsu Ltd | 半導体記憶装置 |
KR100201980B1 (ko) * | 1990-05-14 | 1999-06-15 | 스즈키 진이치로 | 반도체집적회로 |
JPH0430385A (ja) * | 1990-05-25 | 1992-02-03 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
JP3361825B2 (ja) * | 1990-08-22 | 2003-01-07 | テキサス インスツルメンツ インコーポレイテツド | メモリ・アレイ・アーキテクチャ |
JP2664810B2 (ja) * | 1991-03-07 | 1997-10-22 | 株式会社東芝 | メモリセルアレイ分割型半導体記憶装置 |
JP2744144B2 (ja) * | 1991-03-14 | 1998-04-28 | 株式会社東芝 | 半導体記憶装置 |
JPH05250875A (ja) * | 1992-02-27 | 1993-09-28 | Nec Corp | 半導体記憶装置 |
US5742544A (en) * | 1994-04-11 | 1998-04-21 | Mosaid Technologies Incorporated | Wide databus architecture |
KR100240418B1 (ko) * | 1996-12-31 | 2000-03-02 | 윤종용 | 반도체 독출 전용 메모리 및 그의 독출 방법 |
JP4156706B2 (ja) * | 1998-05-29 | 2008-09-24 | 株式会社東芝 | 半導体記憶装置 |
JP2001067898A (ja) * | 1999-08-30 | 2001-03-16 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2002184181A (ja) * | 2000-03-24 | 2002-06-28 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2002170388A (ja) * | 2000-11-30 | 2002-06-14 | Mitsubishi Electric Corp | スタティック型半導体記憶装置 |
JP2007133927A (ja) * | 2005-11-08 | 2007-05-31 | Toshiba Corp | 半導体記憶装置及びその制御方法 |
-
1994
- 1994-04-11 US US08/226,034 patent/US5742544A/en not_active Expired - Lifetime
- 1994-09-28 EP EP94115237A patent/EP0676766B1/de not_active Expired - Lifetime
- 1994-09-28 DE DE69426355T patent/DE69426355T2/de not_active Expired - Lifetime
-
1995
- 1995-04-10 JP JP7084157A patent/JPH0836885A/ja active Pending
-
1997
- 1997-12-08 US US08/986,358 patent/US6195282B1/en not_active Expired - Lifetime
-
2001
- 2001-01-16 US US09/761,297 patent/US6366491B1/en not_active Expired - Lifetime
-
2002
- 2002-01-24 US US10/056,818 patent/US20020067635A1/en not_active Abandoned
- 2002-10-22 US US10/278,195 patent/US6661723B2/en not_active Expired - Fee Related
-
2003
- 2003-10-22 US US10/691,111 patent/US7095666B2/en not_active Expired - Fee Related
-
2006
- 2006-06-28 US US11/476,422 patent/US7486580B2/en not_active Expired - Fee Related
-
2008
- 2008-07-31 US US12/221,195 patent/US7609573B2/en not_active Expired - Fee Related
-
2009
- 2009-09-18 US US12/562,452 patent/US7859930B2/en not_active Expired - Fee Related
-
2010
- 2010-11-23 US US12/952,560 patent/US8218386B2/en not_active Expired - Fee Related
-
2012
- 2012-06-07 US US13/490,700 patent/US8441878B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7486580B2 (en) | 2009-02-03 |
US20110211409A1 (en) | 2011-09-01 |
US8441878B2 (en) | 2013-05-14 |
US20130003478A1 (en) | 2013-01-03 |
US8218386B2 (en) | 2012-07-10 |
US6195282B1 (en) | 2001-02-27 |
EP0676766A2 (de) | 1995-10-11 |
US6661723B2 (en) | 2003-12-09 |
US20030133347A1 (en) | 2003-07-17 |
US5742544A (en) | 1998-04-21 |
US20070047356A1 (en) | 2007-03-01 |
US20090073792A1 (en) | 2009-03-19 |
US7609573B2 (en) | 2009-10-27 |
DE69426355D1 (de) | 2001-01-04 |
US20100128546A1 (en) | 2010-05-27 |
JPH0836885A (ja) | 1996-02-06 |
US7095666B2 (en) | 2006-08-22 |
US20040136226A1 (en) | 2004-07-15 |
US6366491B1 (en) | 2002-04-02 |
US20020067635A1 (en) | 2002-06-06 |
US7859930B2 (en) | 2010-12-28 |
EP0676766A3 (de) | 1995-12-27 |
EP0676766B1 (de) | 2000-11-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |