DE69107463D1 - Integrierte Schaltung, System und Verfahren zur Fehlererzeugung. - Google Patents

Integrierte Schaltung, System und Verfahren zur Fehlererzeugung.

Info

Publication number
DE69107463D1
DE69107463D1 DE69107463T DE69107463T DE69107463D1 DE 69107463 D1 DE69107463 D1 DE 69107463D1 DE 69107463 T DE69107463 T DE 69107463T DE 69107463 T DE69107463 T DE 69107463T DE 69107463 D1 DE69107463 D1 DE 69107463D1
Authority
DE
Germany
Prior art keywords
integrated circuit
error generation
error
generation
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69107463T
Other languages
English (en)
Other versions
DE69107463T2 (de
Inventor
Philip Wilcox
Gudmundur Hjartarson
Robert Hum
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Publication of DE69107463D1 publication Critical patent/DE69107463D1/de
Application granted granted Critical
Publication of DE69107463T2 publication Critical patent/DE69107463T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318566Comparators; Diagnosing the device under test
DE69107463T 1990-09-17 1991-08-19 Integrierte Schaltung, System und Verfahren zur Fehlererzeugung. Expired - Fee Related DE69107463T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/583,208 US5130988A (en) 1990-09-17 1990-09-17 Software verification by fault insertion
PCT/CA1991/000289 WO1992005488A1 (en) 1990-09-17 1991-08-19 Fault insertion

Publications (2)

Publication Number Publication Date
DE69107463D1 true DE69107463D1 (de) 1995-03-23
DE69107463T2 DE69107463T2 (de) 1995-06-14

Family

ID=24332138

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69107463T Expired - Fee Related DE69107463T2 (de) 1990-09-17 1991-08-19 Integrierte Schaltung, System und Verfahren zur Fehlererzeugung.

Country Status (6)

Country Link
US (1) US5130988A (de)
EP (1) EP0549602B1 (de)
JP (1) JP2628105B2 (de)
CA (1) CA2087448C (de)
DE (1) DE69107463T2 (de)
WO (1) WO1992005488A1 (de)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483518A (en) 1992-06-17 1996-01-09 Texas Instruments Incorporated Addressable shadow port and protocol for serial bus networks
US5576980A (en) * 1991-06-28 1996-11-19 Texas Instruments Incorporated Serializer circuit for loading and shifting out digitized analog signals
JP2770617B2 (ja) * 1991-09-05 1998-07-02 日本電気株式会社 テスト回路
US5513188A (en) * 1991-09-10 1996-04-30 Hewlett-Packard Company Enhanced interconnect testing through utilization of board topology data
US5341380A (en) * 1992-03-19 1994-08-23 Nec Corporation Large-scale integrated circuit device
US5640521A (en) * 1992-06-17 1997-06-17 Texas Instruments Incorporated Addressable shadow port and protocol with remote I/O, contol and interrupt ports
FR2693574B1 (fr) * 1992-07-08 1994-09-09 Sgs Thomson Microelectronics Procédé pour tester le fonctionnement d'un circuit intégré spécialisé, et circuit intégré spécialisé s'y rapportant.
JP3563750B2 (ja) * 1992-10-16 2004-09-08 テキサス インスツルメンツ インコーポレイテツド アナログ回路のための走査に基づく試験
EP0642084A1 (de) * 1993-08-04 1995-03-08 Siemens Aktiengesellschaft Integrierte Logikschaltung mit Testmöglichkeit
US5428624A (en) * 1993-10-12 1995-06-27 Storage Technology Corporation Fault injection using boundary scan
US5809036A (en) * 1993-11-29 1998-09-15 Motorola, Inc. Boundary-scan testable system and method
US5600788A (en) * 1994-01-19 1997-02-04 Martin Marietta Corporation Digital test and maintenance architecture
GB2288666B (en) * 1994-04-12 1997-06-25 Advanced Risc Mach Ltd Integrated circuit control
US5642362A (en) * 1994-07-20 1997-06-24 International Business Machines Corporation Scan-based delay tests having enhanced test vector pattern generation
US6243843B1 (en) 1995-01-09 2001-06-05 Agilent Technologies, Inc. Post-mission test method for checking the integrity of a boundary scan test
US5574730A (en) * 1995-01-31 1996-11-12 Unisys Corporation Bussed test access port interface and method for testing and controlling system logic boards
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
US5887001A (en) * 1995-12-13 1999-03-23 Bull Hn Information Systems Inc. Boundary scan architecture analog extension with direct connections
US5668816A (en) * 1996-08-19 1997-09-16 International Business Machines Corporation Method and apparatus for injecting errors into an array built-in self-test
US5938779A (en) * 1997-02-27 1999-08-17 Alcatel Alsthom Compagnie Generale D'electricite Asic control and data retrieval method and apparatus having an internal collateral test interface function
DE69832605T2 (de) * 1997-06-02 2006-08-17 Duaxes Corp. Schnittstellenabtastungselement und kommunikationsvorrichtung die dieses verwendet
NL1006239C2 (nl) * 1997-06-05 1998-12-08 Koninkl Kpn Nv Doorverbindingsinrichting met een electrische of optische signaalbus.
DE19735163A1 (de) * 1997-08-13 1999-03-11 Siemens Ag Integrierter elektronischer Baustein mit Hardware-Fehlereinspeisung für Prüfzwecke
WO1999023503A1 (en) * 1997-10-31 1999-05-14 Koninklijke Philips Electronics N.V. Core test control
US6092226A (en) * 1998-02-10 2000-07-18 Cray Research, Inc. Fabrication of test logic for level sensitive scan on a circuit
US6408413B1 (en) * 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6405335B1 (en) * 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US6327676B1 (en) * 1998-03-31 2001-12-04 Emc Corporation Test equipment
US6536008B1 (en) 1998-10-27 2003-03-18 Logic Vision, Inc. Fault insertion method, boundary scan cells, and integrated circuit for use therewith
US6499124B1 (en) * 1999-05-06 2002-12-24 Xilinx, Inc. Intest security circuit for boundary-scan architecture
DE19961148C1 (de) * 1999-12-17 2001-09-06 Siemens Ag Integrierter elektronischer Baustein zur externen Funktionsbeeinflussung sowie dazugehöriges Verfahren
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US7174492B1 (en) 2001-04-12 2007-02-06 Cisco Technology, Inc. AC coupled line testing using boundary scan test methodology
US6804801B2 (en) * 2001-06-25 2004-10-12 Lucent Technologies Inc. Integrated circuit fault insertion system
DE10204885A1 (de) * 2002-02-06 2003-08-14 Siemens Ag Boundary-Scan mit Modussteuerzellen
US7284159B2 (en) * 2003-08-26 2007-10-16 Lucent Technologies Inc. Fault injection method and system
US7340661B2 (en) * 2003-09-25 2008-03-04 Hitachi Global Storage Technologies Netherlands B.V. Computer program product for performing testing of a simulated storage device within a testing simulation environment
US7165201B2 (en) * 2003-09-25 2007-01-16 Hitachi Global Storage Technologies Netherlands B.V. Method for performing testing of a simulated storage device within a testing simulation environment
DE60314525T2 (de) 2003-12-17 2008-02-28 Stmicroelectronics Ltd., Almondsbury TAP Zeitmultiplexen mit Abtasttest
US7650542B2 (en) * 2004-12-16 2010-01-19 Broadcom Corporation Method and system of using a single EJTAG interface for multiple tap controllers
US7657807B1 (en) * 2005-06-27 2010-02-02 Sun Microsystems, Inc. Integrated circuit with embedded test functionality
US7747901B2 (en) * 2005-07-20 2010-06-29 Texas Instruments Incorporated Auxiliary link control commands
US7689866B2 (en) * 2006-10-18 2010-03-30 Alcatel-Lucent Usa Inc. Method and apparatus for injecting transient hardware faults for software testing
CN100547562C (zh) * 2006-10-18 2009-10-07 国际商业机器公司 自动生成可再现运行时问题的单元测试用例的方法和系统
WO2009013674A1 (en) * 2007-07-20 2009-01-29 Nxp B.V. Automatic address assignment for communication bus
US8073996B2 (en) * 2008-01-09 2011-12-06 Synopsys, Inc. Programmable modular circuit for testing and controlling a system-on-a-chip integrated circuit, and applications thereof
US20110010596A1 (en) * 2009-07-09 2011-01-13 Tao-Yen Yang Testable circuit with input/output cell for standard cell library
US8615693B2 (en) * 2011-08-31 2013-12-24 Lsi Corporation Scan test circuitry comprising scan cells with multiple scan inputs

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4669081A (en) * 1986-02-04 1987-05-26 Raytheon Company LSI fault insertion
US4875209A (en) * 1988-04-04 1989-10-17 Raytheon Company Transient and intermittent fault insertion
DE68928613T2 (de) * 1988-09-07 1998-09-24 Texas Instruments Inc Bidirektionale-Boundary-Scan-Testzelle
JPH02181677A (ja) * 1989-01-06 1990-07-16 Sharp Corp Lsiのテストモード切替方式

Also Published As

Publication number Publication date
WO1992005488A1 (en) 1992-04-02
JPH06500392A (ja) 1994-01-13
EP0549602A1 (de) 1993-07-07
JP2628105B2 (ja) 1997-07-09
DE69107463T2 (de) 1995-06-14
EP0549602B1 (de) 1995-02-15
CA2087448C (en) 1997-05-06
US5130988A (en) 1992-07-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee