CN102694542B - Signal isolation method, device and chip - Google Patents
Signal isolation method, device and chip Download PDFInfo
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- CN102694542B CN102694542B CN201210141650.9A CN201210141650A CN102694542B CN 102694542 B CN102694542 B CN 102694542B CN 201210141650 A CN201210141650 A CN 201210141650A CN 102694542 B CN102694542 B CN 102694542B
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Abstract
The embodiment of the invention discloses signal isolation method, device and chip, the method includes: detect the main power voltage powered for main power source territory, when detecting that described main power voltage is in predeterminated voltage section, produces reset signal；According to described reset signal, produce the first level signal；Control isolating device according to described first level signal and isolate the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into described standby electricity source domain.In technical solution of the present invention, main power source power down can be found in time, and control the signal in isolating device isolation main power source territory, so that the signal in main power source territory cannot be introduced into standby electricity source domain, it is to avoid the signal of standby electricity source domain is produced impact.
Description
Technical field
The present invention relates to chip design art field, particularly relate to signal isolation method, device and chip.
Background technology
When carrying out chip design, generally use multi-power domain design, in order to realize specific circuit function, such as, peace
In the SOC(system on a chip) (SoC, System on Chip) of full chip, two power domain can be set, wherein powered by main power source
Power domain be referred to as main power source territory, generally comprise conventional die logic, such as, central processing unit (CPU, Central
Processing Unit), flash memory (Flash), read only memory (ROM, Read-Only Memory), random access memory
Memorizer (RAM, Random Access Memory) etc., stand-by power supply the power domain powered is referred to as standby electricity source domain,
Generally include nonvolatile random access memory bank (NVRAM, Non-Volatile Random Access Memory) etc., just
In the case of Chang, main power source is power-up state, and stand-by power supply is power-down state, and when main power source accident power down, stand-by power supply
Just becoming power-up state, at this moment stand-by power supply is powered only to standby electricity source domain, thus after main power source power down, permissible
Powered to the NVRAM in standby electricity source domain by stand-by power supply, make NVRAM remain to keep data, during to extend data holding
Between.
In the SoC design scheme of above-mentioned safety chip, although by arranging main power source territory and standby electricity source domain, can lead
After power supply power-fail, stand-by power supply power to standby electricity source domain, but after main power source power down, the signal in main power source territory is still
So can enter standby electricity source domain, thus the signal of standby electricity source domain is produced impact.
Summary of the invention
The embodiment of the present invention provides signal isolation method, device and chip, in order to solve present in prior art
After main power source power down, the signal in main power source territory remains able to enter standby electricity source domain, thus produces the signal of standby electricity source domain
The problem of raw impact.
For solving the problems referred to above, the technical scheme that the embodiment of the present invention provides is as follows:
A kind of signal isolation method, the method includes: detects the main power voltage powered for main power source territory, works as inspection
Measure described main power voltage when being in predeterminated voltage section, produce reset signal；According to described reset signal, produce the
One level signal；Control isolating device according to described first level signal and isolate the signal in described main power source territory, so that described
The signal in main power source territory cannot be introduced into described standby electricity source domain.
A kind of signal isolating device, including: voltage detection unit, for the main power voltage powered for main power source territory is entered
Row detection, when detecting that described main power voltage is in predeterminated voltage section, produces reset signal；First signal produces
Unit, for the reset signal produced according to described voltage detection unit, produces the first level signal；Isolated location, uses
Control isolating device in the first level signal produced according to described first signal generation unit and isolate the letter in described main power source territory
Number, so that the signal in described main power source territory cannot be introduced into described standby electricity source domain.
A kind of chip, including: the main power voltage powered for main power source territory is examined by voltage detector VD, described VD
Survey, when detecting that described main power voltage is in predeterminated voltage section, produce reset signal；Signal isolation circuit, institute
The input of the outfan and described signal isolation circuit of stating VD is connected, and described signal isolation circuit is produced according to described VD
Raw reset signal, produces a level signal；Isolating device, the outfan of described signal isolation circuit and described isolator
The Enable Pin of part is connected, described signal isolation circuit the level signal produced directly controls isolating device and isolates described master
The signal of power domain, so that the signal in described main power source territory cannot be introduced into described standby electricity source domain.
The signal isolation method that embodiment of the present invention technical scheme is provided, by the main power source electricity powered for main power source territory
Pressure detects, it is possible to detect that main power voltage changes in time, and presets electricity detecting that main power voltage is in
During pressure section, produce reset signal, according to this reset signal, produce the first level signal, according to this first level signal
Control isolating device and isolate the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into described standby electricity
Source domain.Therefore, use embodiment of the present invention technical scheme, predeterminated voltage can be in by detection main power voltage
Section, in time discovery main power source power down, and control the signal in isolating device isolation main power source territory, so that main power source territory
Signal cannot be introduced into standby electricity source domain, it is to avoid the signal of standby electricity source domain is produced impact.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to required in embodiment
The accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only some embodiments of the present invention, right
From the point of view of those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other according to these accompanying drawings
Accompanying drawing.
Fig. 1 is in the embodiment of the present invention one, signal isolation method schematic flow sheet；
Fig. 2 is in the embodiment of the present invention two, signal isolating device the first structural representation；
Fig. 3 is in the embodiment of the present invention two, isolated location 23 first structural representation；
Fig. 4 is in the embodiment of the present invention two, isolated location 23 second structural representation；
Fig. 5 is in the embodiment of the present invention two, signal isolating device the second structural representation；
Fig. 6 is in the embodiment of the present invention three, chip the first circuit theory diagrams；
Fig. 7 is in the embodiment of the present invention four, chip second circuit schematic diagram；
Fig. 8 is in the embodiment of the present invention five, chip tertiary circuit schematic diagram；
Fig. 9 is in the embodiment of the present invention five, main power source, reset signal and the sequential chart of isolation signals；
Figure 10 is in the embodiment of the present invention six, chip the 4th circuit theory diagrams；
Figure 11 is in the embodiment of the present invention, a kind of overall chip composition schematic diagram.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete retouching
State, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on the present invention
In embodiment, the every other embodiment that those of ordinary skill in the art are obtained under not making creative work premise,
Broadly fall into the scope of protection of the invention.
Embodiment one
As it is shown in figure 1, be the signal isolation method schematic flow sheet of the embodiment of the present invention one proposition, its concrete handling process
As follows:
Step 11, detects the main power voltage powered for main power source territory, when detecting that described main power voltage is in
During predeterminated voltage section, produce reset signal.
Wherein it is possible to by original voltage detecting (VD, Voltage Detector) module or electrification reset in chip
Main power voltage is detected by (PoR, Power on Reset) module.
In the embodiment of the present invention one, above-mentioned predeterminated voltage section can be set in advance as a magnitude of voltage, such as 2.55 volts,
A voltage range, such as, 2.55～2.15V can also be set in advance as.
Step 12, according to reset signal, produces the first level signal.
Above-mentioned reset signal can be received by the reset terminal of basic circuit unit triggers device (flip-flop),
After the reset terminal of flip-flop receives reset signal, the outfan of flip-flop produce the first level signal, this
Time, above-mentioned first level signal is low level signal.
Step 13, controls isolating device according to the first level signal and isolates the signal in described main power source territory, so that main power source territory
Signal cannot be introduced into standby electricity source domain.
Wherein it is possible to directly controlled the signal in isolating device isolation main power source territory by above-mentioned first level signal, so that described
The signal in main power source territory cannot be introduced into described standby electricity source domain, it is also possible to after processing above-mentioned first level signal, then
The signal in isolating device isolation main power source territory is controlled by the signal after processing.
In the embodiment of the present invention one, the processing mode of above-mentioned first level signal be can be, but not limited to following two kinds:
The first processing mode, carries out voltage holding process to the first level signal, produces second electrical level signal, by second
Level signal directly controls the signal in isolating device isolation main power source territory, so that the signal in main power source territory cannot be introduced into standby electricity
Source domain.
Owing to, after main power source power down completes, the first level signal produced by step 12 is it may happen that change, such as
Become high-impedance state from low level signal, above-mentioned first level signal directly control the letter in isolating device isolation main power source territory
Number reliability relatively low, in the embodiment of the present invention one, by use the first processing mode above-mentioned first level signal is entered
After row voltage holding processes, can be after main power source power down complete, second electrical level signal remains in that stable low level letter
Number, this second electrical level signal the reliability of the signal controlling isolating device isolation main power source territory is higher.
The second processing mode, first carries out voltage holding process, produces three level signal, then the first level signal
Three level signal is carried out voltage stabilizing process, produces the 4th level signal, the 4th level signal directly control isolating device
The signal in isolation main power source territory, so that the signal in main power source territory cannot be introduced into standby electricity source domain.
Owing to using the first processing mode, after the first level signal is carried out voltage holding process, the second electrical level obtained
Signal, in this case it is still possible to there is the situation of voltage instability, after making main power source power down, it is possible to produces stable level letter
Number controlling isolating device comes into force, and can use the second processing mode, due in the second processing mode, to the first electricity
Ordinary mail number voltage to be carried out holding process, also to carry out voltage stabilizing process to the three level signal produced, therefore enter one
Step strengthens the stability of level signal, thus the 4th level signal after being processed by voltage stabilizing controls the isolating device main electricity of isolation
The reliability of the signal of source domain is higher.
Additionally, in order to ensure after main power source powers on, make the signal in main power source territory enter standby electricity source domain, journey to be passed through
Sequence sets, and is produced an input signal by CPU after main power source powers on, after receiving the input signal that CPU produces,
Produce the 5th level signal, control isolating device bypass according to the 5th level signal, enable the signal in main power source territory to enter
Standby electricity source domain.
Above-mentioned 5th level signal should be believed with the first level signal, second electrical level signal, three level signal and the 4th level
Number signal condition different, such as, if the first level signal, second electrical level signal, three level signal and the 4th level
Signal is low level signal, then the 5th level signal can be high level signal.
From above-mentioned processing procedure, use the signal isolation method of the embodiment of the present invention one, by supplying for main power source territory
The main power voltage of electricity detects, it is possible to detect that main power voltage changes in time, and is detecting main power source electricity
When pressure is in predeterminated voltage section, produces reset signal, according to this reset signal, produce the first level signal, according to this
First level signal controls isolating device and isolates the signal in described main power source territory, so that the signal in described main power source territory cannot enter
Enter described standby electricity source domain.Therefore, use the technical scheme of the embodiment of the present invention one, can be by detection main power source
Voltage is in predeterminated voltage section, in time discovery main power source power down, and controls the signal in isolating device isolation main power source territory,
So that the signal in main power source territory cannot be introduced into standby electricity source domain, it is to avoid the signal of standby electricity source domain is produced impact.
Embodiment two
Accordingly, the embodiment of the present invention two provides a kind of signal isolating device, and its structure is as in figure 2 it is shown, include:
Voltage detection unit 21, for detecting the main power voltage powered for main power source territory, when detecting described master
When supply voltage is in predeterminated voltage section, produce reset signal；
First signal generation unit 22, for the reset signal produced according to described voltage detection unit 21, produces first
Level signal；
Isolated location 23, controls isolator for the first level signal produced according to described first signal generation unit 22
Part isolates the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into described standby electricity source domain.
It is preferred that described isolated location 23 is specifically for the first level of being produced by described first signal generation unit 22
Signal directly controls isolating device and isolates the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into institute
State standby electricity source domain.
It is preferred that the embodiment of the present invention two provides a kind of isolated location 23, its structure is as it is shown on figure 3, isolated location 23
Including:
Secondary signal generating subunit 231, enters for the first level signal producing described first signal generation unit 22
Row voltage holding processes, and produces second electrical level signal；
First separaant unit 232 is straight for the second electrical level signal produced by described secondary signal generating subunit 231
Connect the signal controlling the described main power source territory of isolating device isolation, so that the signal in described main power source territory cannot be introduced into described standby
Power domain.
It is preferred that the embodiment of the present invention two provides another kind of isolated location 23, its structure as shown in Figure 4, isolated location
23 include:
3rd signal generating subunit 233, enters for the first level signal producing described first signal generation unit 22
Row voltage holding processes, and produces three level signal；
4th signal generating subunit 234, for the 3rd level letter producing described 3rd signal generating subunit 233
Number carry out voltage stabilizing process, produce the 4th level signal；
Second separaant unit 235 is straight for the 4th level signal produced by described 4th signal generating subunit 234
Connect the signal controlling the described main power source territory of isolating device isolation, so that the signal in described main power source territory cannot be introduced into described standby
Power domain.
It is preferred that the embodiment of the present invention two provides another kind of signal isolating device, its structure is as it is shown in figure 5, include:
Voltage detection unit 51, for detecting the main power voltage powered for main power source territory, when detecting described master
When supply voltage is in predeterminated voltage section, produce reset signal；
First signal generation unit 52, for the reset signal produced according to described voltage detection unit 51, produces first
Level signal；
Isolated location 53, controls isolator for the first level signal produced according to described first signal generation unit 52
Part isolates the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into described standby electricity source domain；
5th signal generation unit 54, for after receiving the input signal that CPU produces, produces the 5th level signal；
Control unit 55, controls isolator for the 5th level signal produced according to described 5th signal generation unit 54
Part, makes the signal in described main power source territory enter described standby electricity source domain.
Use the signal isolating device that the embodiment of the present invention two provides, first supplied for main power source territory by voltage detection unit 21
The main power voltage of electricity detects, it is possible to detect that main power voltage changes in time, and is detecting main power source electricity
When pressure is in predeterminated voltage section, produce reset signal, then by the first signal generation unit 22 according to voltage detection unit
21 reset signals produced, produce the first level signal, then are produced according to the first signal generation unit 22 by isolated location 23
The first raw level signal controls isolating device and isolates the signal in described main power source territory so that the signal in described main power source territory without
Method enters described standby electricity source domain.Therefore, use embodiment of the present invention technical scheme, voltage detecting list can be passed through
Unit 21 detection main power voltage is in predeterminated voltage section, finds main power source power down in time, and is controlled by isolated location 23
The signal in isolating device isolation main power source territory, so that the signal in main power source territory cannot be introduced into standby electricity source domain, it is to avoid right
The signal of standby electricity source domain produces impact.
Embodiment three
Accordingly, the embodiment of the present invention three provides a kind of chip, its circuit theory diagrams as shown in Figure 6, including:
The main power voltage powered for main power source territory is detected by VD, described VD, when detecting described main power voltage
When being in predeterminated voltage section, produce reset signal；
Signal isolation circuit, the outfan of described VD is connected with the input of described signal isolation circuit, described signal
The reset signal that isolation circuit produces according to described VD, produces a level signal；
Isolating device, the outfan of described signal isolation circuit is connected with the Enable Pin of described isolating device, by described letter
Number level signal that isolation circuit produces directly controls isolating device and isolates the signal in described main power source territory, so that described main electricity
The signal of source domain cannot be introduced into described standby electricity source domain.
After making main power source power on, control isolating device bypass, make the signal in main power source territory enter standby electricity source domain, can
To utilize the CPU pre-set in main power source territory, the input of described signal isolation circuit is connected with described cpu bus,
After the main power source powered for main power source territory powers on, described CPU control described signal isolation circuit, produce a level letter
Number；The level signal produced by described signal isolation circuit controls isolating device and turns on the signal in described main power source territory, makes institute
The signal stating main power source territory enters described standby electricity source domain.
Wherein, VD also can be substituted by PoR, detects main power voltage, when detecting that described main power voltage is in
During predeterminated voltage section, produce reset signal.
Embodiment four
Accordingly, the embodiment of the present invention four provides another kind of chip, and its circuit theory diagrams are as it is shown in fig. 7, signal isolation is electric
Road includes: a flip-flop, and the outfan of described VD is connected with the reset terminal of a described flip-flop, institute
State the reset signal that a flip-flop produces according to described VD, produce a level signal, a described flip-flop
Outfan be connected with the Enable Pin of described isolating device, by described oneth flip-flop produce level signal direct
Control isolating device and isolate the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into described standby electricity
Source domain.
Embodiment five
Accordingly, the embodiment of the present invention five provides another kind of chip, and as shown in Figure 8, signal isolation is electric for its circuit theory diagrams
Road includes: a flip-flop, and the outfan of described VD is connected with the reset terminal of a described flip-flop, institute
State the reset signal that a flip-flop produces according to described VD, produce a level signal；First bus level keeps single
Unit Bushold, the outfan of a described flip-flop is connected with the input of a described Bushold, described
The level signal that a described flip-flop is produced by the oneth Bushold carries out voltage holding process, produces a level letter
Number, the described outfan of a Bushold is connected with the Enable Pin of described isolating device, by a described Bushold
The level signal produced directly controls isolating device and isolates the signal in described main power source territory, so that the signal in described main power source territory
Cannot be introduced into described standby electricity source domain.
Wherein, in order to make circuit structure compact, when specific design chip, a VD and flip-flop can be placed in
In main power source territory, a Bushold is placed in standby electricity source domain.
As it is shown in figure 9, be in the embodiment of the present invention five, main power source VCC, reset signal and the sequential chart of isolation signals,
The signal how chip shown in Fig. 8 realizes isolating main power source territory below in conjunction with this sequential chart is specifically described.
Under VCC in electric process, VD drives reset signal to be low level, causes the level signal of a flip-flop to become
For low level, and then to drive the level signal upset of a Bushold be low level, makes isolating device come into force, i.e. controls
The signal in isolating device isolation main power source territory, so that the signal in main power source territory cannot be introduced into standby electricity source domain.VCC power down is complete
Cheng Hou, the level signal of a flip-flop becomes high-impedance state, and the level signal of a Bushold may proceed to keep
Low level, makes isolating device come into force.After VCC re-powers, program the oneth flip-flop is set by cpu bus
Input signal be high level, and then drive the level signal of a flip-flop and the level signal of a Bushold
Become high level, so that isolating device bypass, even if the signal in main power source territory enters standby electricity source domain.
Embodiment six
Accordingly, the embodiment of the present invention six provides another chip, and its circuit theory diagrams as shown in Figure 10, isolate by signal
Circuit includes: a flip-flop, and the outfan of described VD is connected with the reset terminal of a described flip-flop,
The reset signal that a described flip-flop produces according to described VD, produces a level signal；First bus level keeps
Unit B ushold, the outfan of a described flip-flop is connected with the input of a described Bushold, institute
State a Bushold and the level signal of a described flip-flop generation is carried out voltage holding process, produce a level
Signal；2nd flip-flop, the outfan of described VD is connected with the reset terminal of described 2nd flip-flop, described
After 2nd flip-flop receives the reset signal that described VD produces, produce a level signal；2nd Bushold, institute
The input of the outfan and described 2nd Bushold of stating the 2nd flip-flop is connected, the described 2nd Bushold pair
The level signal that described 2nd flip-flop produces carries out voltage holding process, produces a level signal；3rd
Flip-flop, the outfan of a described Bushold is connected with the clock end of described 3rd flip-flop, and described
The outfan of two Bushold is connected with the reset terminal of described 3rd flip-flop, described 3rd flip-flop according to
The level signal that a described Bushold is produced by the level signal that described 2nd Bushold produces carries out voltage stabilizing process,
Producing a level signal, described isolating device is connected with the outfan of described 3rd flip-flop, by the described 3rd
The level signal that fl ip-flop produces directly controls isolating device and isolates the signal in described main power source territory, so that described main electricity
The signal of source domain cannot be introduced into described standby electricity source domain.
Wherein, in order to circuit structure is compact, when specific design chip, can be by VD, a flip-flop and second
Fl ip-flop is placed in main power source territory, is placed in standby by a Bushold, the 2nd Bushold and the 3rd flip-flop
In power domain.
Using the signal isolation circuit of the embodiment of the present invention six, the input of the 3rd flip-flop is fixing connects high level.This
Sample, under VCC in electric process, VD produces reset signal and drives the 2nd flip-flop output low level signal, through second
After Bushold output low level signal, drive the 3rd flip-flop reset output low level signal.By increasing the 3rd
Flip-flop can strengthen to produce and stablize the reliability of low level signal, time electric under VCC, and a Bushold and the
Two Bushold equal output low level signal, when only the two occurs unstable simultaneously, just can interfere with the 3rd flip-flop
Level signal.After under VCC, electricity terminates, even if a Bushold and the 2nd Bushold there being one shakiness occurs
Fixed, do not interfere with the 3rd flip-flop output low level signal yet.After VCC re-powers, program is by setting first
The input signal of flip-flop be the input signal of high level and the 2nd flip-flop be high level, the 3rd can be made
Flip-flop exports high level signal, makes isolating device bypass.
The signal isolation circuit that the embodiment of the present invention is proposed, based on digital circuit and analog circuit co-design, has knot
Structure is simple, it is easy to be integrated into chip, the advantages such as technological parameter is insensitive.
As shown in figure 11, in the embodiment of the present invention, a kind of overall chip forms schematic diagram, comprises power domain 1 and electricity
Source domain 2, wherein, power domain 1 is powered by main power source VCC, can be referred to as main power source territory, and power domain 2 is by stand-by power supply
VBAT powers, and can be referred to as standby electricity source domain.Main power source comprises CPU in territory, it is also possible to comprise direct memory access (DMA,
Direct Memory Access) memorizer, Flash, RAM and NVRAM controller etc., standby electricity source domain can be wrapped
Containing low pressure difference linear voltage regulator (LDO, low dropout regulator), control circuit and NVRAM etc..Isolating device
Be connected between main power source territory and standby electricity source domain, for isolating the signal in main power source territory so that the signal in main power source territory without
Method enters standby electricity source domain, after can avoiding the power down of main power source territory, standby electricity source domain is produced impact.Signal isolation circuit
Reset terminal be connected with the outfan of VD, the outfan of signal isolation circuit is connected with the Enable Pin of isolating device, use
Signal isolation is realized with isolating device in matching.
The chip that the embodiment of the present invention is provided, may be used for realizing the signal isolation method that the embodiment of the present invention is provided.
Professional can also further should be able to be it is realized that combine the list of each example that the embodiments described herein describes
Unit and algorithm steps, it is possible to electronic hardware, computer software or the two be implemented in combination in, in order to clearly demonstrate
The interchangeability of hardware and software, the most generally describes composition and the step of each example according to function
Suddenly.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme
Condition.Professional and technical personnel can use different methods to realize described function to each specifically should being used for, but
This realization is it is not considered that exceed the scope of the embodiment of the present invention.
The method described in conjunction with the embodiments described herein or the step of algorithm can directly use hardware, processor to perform
Software module, or the combination of the two implements.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses the present invention to implement
Example.Multiple amendment to these embodiments will be apparent from for those skilled in the art, herein institute
The General Principle of definition can be real in other embodiments in the case of without departing from the spirit or scope of the embodiment of the present invention
Existing.Therefore, the embodiment of the present invention is not intended to be limited to the embodiments shown herein, and is to fit to and institute herein
Disclosed principle and the consistent the widest scope of features of novelty.
The foregoing is only the preferred embodiment of the embodiment of the present invention, not in order to limit the embodiment of the present invention, all
Within the spirit of the embodiment of the present invention and principle, any modification, equivalent substitution and improvement etc. made, should be included in this
Within the protection domain of inventive embodiments.
Claims (4)
1. a signal isolation method, it is characterised in that including:
Detecting the main power voltage powered for main power source territory, when detecting that described main power voltage is in predeterminated voltage section, produce reset signal, described main power source territory is powered by the main power source of SOC(system on a chip) SoC；
According to described reset signal, produce the first level signal；
Control isolating device according to described first level signal and isolate the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into standby electricity source domain；
Described method also includes:
After receiving the input signal that central processor CPU produces, produce the 5th level signal；
Control isolating device according to described 5th level signal, make the signal in described main power source territory enter described standby electricity source domain；
Wherein, the described signal controlling the described main power source territory of isolating device isolation according to described first level signal, so that the signal in described main power source territory cannot be introduced into described standby electricity source domain, including:
Described first level signal is carried out voltage holding process, produces second electrical level signal；
Directly controlled isolating device by described second electrical level signal and isolate the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into described standby electricity source domain；Or,
Described first level signal is carried out voltage holding process, produces three level signal；
Described three level signal is carried out voltage stabilizing process, produces the 4th level signal；
Directly controlled isolating device by described 4th level signal and isolate the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into described standby electricity source domain.
2. a signal isolating device, it is characterised in that including:
Voltage detection unit, for detecting the main power voltage powered for main power source territory, when detecting that described main power voltage is in predeterminated voltage section, produces reset signal, and described main power source territory is powered by the main power source of SOC(system on a chip) SoC；
First signal generation unit, for the reset signal produced according to described voltage detection unit, produces the first level signal；
Isolated location, the first level signal for producing according to described first signal generation unit controls isolating device and isolates the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into standby electricity source domain；
Also include:
5th signal generation unit, for after receiving the input signal that central processor CPU produces, produces the 5th level signal；
Control unit, controls isolating device for the 5th level signal produced according to described 5th signal generation unit, makes the signal in described main power source territory enter described standby electricity source domain；
Wherein, described isolated location specifically for: by described first signal generation unit produce the first level signal directly control isolating device isolate described main power source territory signal so that the signal in described main power source territory cannot be introduced into described standby electricity source domain；Or,
Described isolated location includes:
Secondary signal generating subunit, carries out voltage holding process for the first level signal producing described first signal generation unit, produces second electrical level signal；
First separaant unit, the second electrical level signal for being produced by described secondary signal generating subunit directly controls isolating device and isolates the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into described standby electricity source domain；Or,
Described isolated location includes:
3rd signal generating subunit, carries out voltage holding process for the first level signal producing described first signal generation unit, produces three level signal；
4th signal generating subunit, carries out voltage stabilizing process for the three level signal producing described 3rd signal generating subunit, produces the 4th level signal；
Second separaant unit, the 4th level signal for being produced by described 4th signal generating subunit directly controls isolating device and isolates the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into described standby electricity source domain.
3. a chip, it is characterised in that including:
The main power voltage powered for main power source territory is detected by voltage detector VD, described VD, when detecting that described main power voltage is in predeterminated voltage section, produces reset signal；Described main power source territory is powered by the main power source of SOC(system on a chip) SoC；
Signal isolation circuit, the outfan of described VD is connected with the reset terminal of described signal isolation circuit, and the reset signal that described signal isolation circuit produces according to described VD produces a level signal；
Isolating device, the outfan of described signal isolation circuit is connected with the Enable Pin of described isolating device, the level signal produced by described signal isolation circuit directly controls isolating device and isolates the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into standby electricity source domain；
Wherein, described signal isolation circuit includes:
First basic circuit unit triggers device flip-flop, the outfan of described VD is connected with the reset terminal of a described flip-flop, the reset signal that a described flip-flop produces according to described VD, produce a level signal, the described outfan of a flip-flop is connected with the Enable Pin of described isolating device, the level signal produced by a described flip-flop directly controls isolating device and isolates the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into described standby electricity source domain；
Described signal isolation circuit also includes:
First bus level holding unit Bushold, the outfan of a described flip-flop is connected with the input of a described Bushold, the level signal that a described flip-flop is produced by a described Bushold carries out voltage holding process, produce a level signal, the described outfan of a Bushold is connected with the Enable Pin of described isolating device, the level signal produced by a described Bushold directly controls isolating device and isolates the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into described standby electricity source domain；
Described signal isolation circuit also includes:
2nd flip-flop, the outfan of described VD is connected with the reset terminal of described 2nd flip-flop, after described 2nd flip-flop receives the reset signal that described VD produces, produces a level signal；
2nd Bushold, the outfan of described 2nd flip-flop is connected with the input of described 2nd Bushold, and the level signal that described 2nd flip-flop is produced by described 2nd Bushold carries out voltage holding process, produces a level signal；
3rd flip-flop, the outfan of a described Bushold is connected with the clock end of described 3rd flip-flop, the outfan of described 2nd Bushold is connected with the reset terminal of described 3rd flip-flop, the level signal that a described Bushold is produced by the level signal that described 3rd flip-flop produces according to described 2nd Bushold carries out voltage stabilizing process, produce a level signal, described isolating device is connected with the outfan of described 3rd flip-flop, the level signal produced by described 3rd flip-flop directly controls isolating device and isolates the signal in described main power source territory, so that the signal in described main power source territory cannot be introduced into described standby electricity source domain.
4. chip as claimed in claim 3, it is characterised in that also include:
Central processor CPU, described CPU is placed in main power source territory, the input of described signal isolation circuit is connected with described cpu bus, after the main power source powered for main power source territory powers on, described signal isolation circuit is controlled by described CPU, produce a level signal, described signal isolation circuit the level signal produced controls isolating device and turns on the signal in described main power source territory, makes the signal in described main power source territory enter described standby electricity source domain.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103884981B (en) * | 2014-04-16 | 2016-11-02 | 威盛电子股份有限公司 | Isolation circuit |
| CN105577170B (en) * | 2015-12-25 | 2018-09-14 | 无锡华大国奇科技有限公司 | Isolation control circuit |
| US10601217B2 (en) * | 2017-04-27 | 2020-03-24 | Qualcomm Incorporated | Methods for detecting an imminent power failure in time to protect local design state |
| CN108958445A (en) * | 2017-05-19 | 2018-12-07 | 华大半导体有限公司 | Spare area and electronic system |
| CN108958985A (en) * | 2017-05-19 | 2018-12-07 | 华大半导体有限公司 | Chip |
| GB2566445B8 (en) * | 2017-09-06 | 2020-03-04 | Advanced Risc Mach Ltd | Reset isolation bridge |
| CN111258404A (en) * | 2018-12-03 | 2020-06-09 | 珠海格力电器股份有限公司 | Isolation circuit system and method for signal isolation |
| CN113330388B (en) * | 2019-12-30 | 2023-06-13 | 成都海光集成电路设计有限公司 | Chip design method, chip design device, chip and electronic equipment |
| CN112073050B (en) * | 2020-11-12 | 2021-02-09 | 杭州晶华微电子有限公司 | Power supply power-on reset circuit for semiconductor integrated circuit |
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