CA2087448C - Fault insertion - Google Patents

Fault insertion

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Publication number
CA2087448C
CA2087448C CA002087448A CA2087448A CA2087448C CA 2087448 C CA2087448 C CA 2087448C CA 002087448 A CA002087448 A CA 002087448A CA 2087448 A CA2087448 A CA 2087448A CA 2087448 C CA2087448 C CA 2087448C
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CA
Canada
Prior art keywords
output
input
selector
scan
integrated circuit
Prior art date
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Expired - Fee Related
Application number
CA002087448A
Other languages
French (fr)
Inventor
Philip Stanley Wilcox
Gudmundur Albert Hjartarson
Robert Andreas Hum
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
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Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
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Publication of CA2087448C publication Critical patent/CA2087448C/en
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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318566Comparators; Diagnosing the device under test

Abstract

An integrated circuit 11 12, 13, 14) having boundary-scan facilities in accordance with IEEE Standard 1149.1, has its boun-dary scan chain configured to permit fault insertion testing of di-agnostic and maintenance software. Each scan cell (39, 40, 45, 46) includes storage devices for storing a pair of bits of a binary vec-tor shifted into the boundary scan chain. One bit comprises faulty data and the other bit serves to control application of the faulty data by the scan cell. A system incorporating such integrated cir-cuits includes a controller (23) for controlling the IEEE test inter-face to shift the binary vector into the boundary scan chain, and diagnostic and maintenance software (21) for diagnosing the faults introduced into the integrated circuits.

Description

WO 92/05488 ~ PCr/CA91/00289 ~ 2~87~48 Fault lnsertion.
DESCRIPTIO'`J
TECHNICAL FIELD:
This invention relates to a method and apparatus f or testing integrated circuits and systems or ~nodules incu.~o-~ting integrated circuits. The inventi on is P~re~ i ~ l l y applicable to fault in5ertion testing of diagnostic software in such systems of inteqrated circuits.
BAc~ )uNU ART:
Increasing complexity of integrated circuit:s and increasing use of surface mount int.:r-ul.lle~_Lion technology have led manufacturers of such integrated circuits to design 15 them for easier testing using technigues such as the so-called "boundary scan" technique. It has been proposed to provide for standardized access to such integrated circuits for test purposes. The resulting standard, IEEE standard 1149.1, def ines a standard serial bus access method employing the 20 "boundary scan" technique which provides total control over an integrated circuit ' s input and output pins . This standard serial bus interface permits control of all of the integrated circuit's input/output operations, in-lPpPn~Pntly of the integrated circuit's function, and while the system i~; in its 25 operating mode.
Boundary scan arr~n~ - ts have been disclosed in the following papers: Colin Maundar and Frans Beenker, "BOUNDARY-SCAN: A Framework For Structured Design-For-Test, " IEEE
International Test Conference February 1987; Patrick P.
30 Fasang, 'iBoundary Scan And Its Application To Analog-Digital ASIC Testing in a Board/System Environment, " IEEE Custom Integrated Circuits Conference 1989.
Boundary scan integrated circuits compatible wi th IEEE
1149.1 comprise a scan cell in the signal path betw~en each 35 bonding pad or terminal and the core circuitry of the integrated circuit. In this specification, the term "core circuitry" refers to circuitry which is internal to the integrated circuit and which is to be tested. The sc.~ cells --WO 92~0~;488 ! 2 0 ~ 7 4 4 8 PCT/CA91/00289 ~r 2 are connected in series, i.e. in a chain, to a four wire interface known as the TAP interface, which permits access to the scan chain for testing purposes. The TAP interface comprises a series of shift registers, one to store 5 instructions and the others to store test data to be used in accordance with those instructions. The scan chain comprises an external shift register connected between TAP interface ports .
Each scan cell comprises a storage device and a switch.
10 In normal operation the switch connects the core circuitry to the pad or terminal to allow passage of normal functional signals. For test ~u-~oses, the switch connects the t-~rTninAl pad or the core circuitry to the storage device . A ref erence - binary vector stqred in the chain of storage devices can thus 15 be applied to the core circuitry or to the ~c~rmin;~l pads of the integrated circuit.
This IEEE standard boundary scan design facilitates the testing of hardware, but is not entirely satisfactory for use when testing software, particularly diagnostic and maintenance 20 software for monitoring the system's performance. Large and complex systems, such as telephone switches and data transmission equipment, have substantial portions of their operating software dedicated to maintenance and diagnostic functions. Typically, such systems are able to diagnose 25 problems and, in some cases, initiate r ~ l action.
The maintenance and diagnostic software packages themselves are large, complex and vital systems. It is nPc~Cc;lry to be able to test and verify the operation of these software packages. One way of doing 50 is to introduce faults 30 delIberately into the hardware, see if they are detected and, where applicable, ensure that appropriate corrective action is taken. This procedure is known as "Fault Insertion".
Clearly f ault insertion must be done with the system in its normal operating configuration. Examples of fault insertion 35 systems are disclosed in U.5. patent number 4,669,081 dated ~ay 26, 1987, inventors James X. Mathewes, Jr. et al and U.S.
patent number 4,875,209 dated October 17, 1989, inventors James K. Mathewes, Jr. et al. Such fault insertion techniques .~ .
_ _ . _ . _ .. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .. . .

generally are difficult to perform with adequate thoroughness in view of the size of the hardware systems involved (many thmlcAnfl~:: of nodes to which faults are to be applied) and the density of the packaging.
It is desirable to be able to use fault insertion testing in systems which employ IEEE standard 1149.1. Unfortunately, this is not possible because the IEEE standard 1149.1 boundary ~can system does not easily permit individual input or output terminals of the integrated circuit to be A~-c~csPd 10 independently. Consequently, if a fault were to be inserted, all t~rm;nAlt: would be affected and the integrated circuit would simply not function at all.
An object of the present invention is to provide a testing arrangement for integrated circuits and/or for modules 15 or systems including integrated circuits, which is compatible with the aforementioned IEEE standard 1149.1 bu1: also facilitates fault insertion testing of associated software.
DISCLOSURE OF INVENTION:
According to one aspect of the present invention, there is provided an integrated circuit comprising a test interface, a plurality of t~rm~nAl pads, a corrPcpr~n~lin~ plurality of scan cells each connected to a respective one oi~ said plurality oia terminAl pads, and core circuitry, each scan cell 25 comprising an input and an output connected one to a said t~rminAl pad and the other to said core circuitry, storage means and selector means, said storage means of each scan cell being connected, in series with the corresponding storage means of the I~ ~ i n~or 30 of said plurality of scan cells, between an input port and an output port of said test interface, said test interface comprising means for loading into the series of storage means a binary vector comprising a series of pairs of binary bits;
each storage means for storing a said pair of binary bits, one of said pair of binary bits comprising a faulty data bit to be applied to said output of said scan cell, the other of said pair of binary bits serving to control application of _ _ _ _ _ _ _ . . . . _ _ . . _ _ _ _ _ .

4 2()87448 said one of said pair of binary bits to the output of the 5can cell, each selector means being responsive to a control signal, a trigger signal and said other of said pair of bits for 5 selectively connecting either of said input of said scan cell and the output of said storage means to said output of said scan cell, the arrangement being such that application of said faulty data to said scan cell output is dPpP~lPnt upon the state of said other of said pair of bits.
According to a second aspect of the invention, t]lere is provided a system comprising at least one integrated circuit, the integrated circuit comprising a test interface, a plurality of tPrm;nAl pads, a corrPspon~lin~ plurality of scan cells each connected to a respective one of said plurality of 15 term;nAl pads, and core circuitry, said scan cells each comprising storage means for storing a pair of bits, one of said pair of bits comprising a faulty data bit and the other of said pair of bits comprising an enabling bit; the plurality of storage means being connected in series between a scan 20 input port and a scan output port of said test interface, said test interface being operable to load a binary vector into selected ones of the series-connected storage means, said binary vector comprising a corresponding series of pairs of binary bits, each pair of binary bits comprising, alternately, 25 a said faulty data bit and a said enabling bit, each enabling bit for controlling application of a said faulty data bit by a said scan cell, said system further comprising controller means for controlling said test interface to provide a control signal and a trigger signal, each scan cell further comprising 30 an input and an output connected one to a said tPrm;nAl pad and the other to said core circuitry, and selector means re~ponsive to said control signal, said trigger signal and said enabling bit for selectively connecting either said input of said scan cell or its said storage means to said output of 35 said scan cell, the arrangement being such that said faulty data bit is applied as the output of said scan cell in dependence upon the state of said enabling bit.

20~74~8 In preferred ` ';r^ntS of the invention, the system include6 means for diagnosing faulty data bits.
According to a third aspect of the invention, t]qere is provided a method of testing an integrated circuit of the 5 f irst aspect . The method comprises the steps of (i) loading a binary vector into said serie6 of ~torage means such that each individual storage means holds a pair of bits, one bit comprising a faulty data bit and the other bit comprising an enabling bit, and applying a trigger signal to 10 said selector means to initiate application of said faulty data bit to the output of said scan cell in ~l~p~n~l~n~e upon the state of said other bit of said pair of bits.
BRIEF DESCRIPTION OF n~wTNr-~c An embodiment of the invention will now be described by way of example only and with reference to the ~-c -nying drawings in which:
Figure 1 is a schematic block diagram of a system comprising several integrated circuits grouped in a module 20 each of the integrated circuits having scan cells for use in bo ~

,, ,~ ,.

5 ~D~7~1g8 Figure 2 illustrates the boundary scan component~; of one of the integrated circuit in more detail; and Figure 3 is a detail view of a modified scan ce] l.
5 MODE(S) FOR CARRYING OUT THE INVENTION:
Referring now to Figure 1, which is a much simplified illustration of a digital electronics system, a module 10 comprises four integrated circuits 11 - 14, respec:tively.
Although only four are shown for the purposes of this 10 description, there might be more, or fewer, in a typical system. The integrated circuits 11-14 are connectlsd to a mi~;Lu~locessu~ 15 by way of a functional bus 16. The miL:LU~IUCessUL 15 is connected to a memory 17, software store 18, and a user interface 19. The miC:LU~LUCess~L 15 employs 15 ~LUyLa~,a from store 18 to control the module 10 by way of functional bus 16. In operation, operating software 20 will control the normal operation of the system, for example to handle tPl ~rh~mP calls. Diagnostic and maintenance ~oftware 21 will monitor the operation of the system, and E~ossibly 20 initiate ~ ;A1 action if a fault occurs. Fault insertion software 22 will be employed, as described in more detail later, to test the operation of the diagnostic and maintenance software 21.
The mi~L~ ocessor 15 is also connected to the mc~dule lO
25 by way of an IEEE 1149.1 test bus controller 23 to which it is connected by a bus 24. It will be appreciated tha~t there will be various ir~Lt!rcù~-l-eu-ions both between the integrated circuits and to other ~ -nPnts of the system. To simplify the description, however, only connections relevant to the 3 o testing of the integrated circuits are shown .
A suitable test bus controller 23 and associated software - are marketed as a package by Texas Ina LL I ts Inc . under the trade mark ASSET . The package comprises a card f or insertion into a personal computer and software to allow the card to 35 communicate with integrated circuits having a so-called TAP
interface configured in accordance with IEEE Standard 1149.1.
The integrated circuits 11-14 have TAP interfaces 25 to 28, respectively, each having clock, mode select, data in and data . . , . .. .. . . . . _ _ . _ _ . . _ _ WO 92/0~488 PCT/CA91/00289 4~8 6 out ports . The TAP lnterf aces communicate with the test bus controller 23 by a four-wire bus 29.
A serial "scan" bus segment 30 connects a aata output of test bus controller 23 to a data input of integrated circuit 5 11. CoLLe~yul~ding serial bus segments 31, 32, 33 and 34 connect the integrated circuits 11 to 14 in daisy-chain fashion to a data-in port of test bus controller 23. The TAP
interfaces 25-28 each comprise 6hift registers connected between their data-in and data-out ports to receive data under 10 the control of the clock (CLK) and mode select ~TMS) signals.
one of these shift reqisters is for storing instruction sequences from the test bus controller 23. The integrated circuits 11-14 have boundary scan chains of storage devices 35-38, respectively, also connected between the "data-in" and 15 "data-out" ports of their TAP interfaces 25-28, respectively.
Each of the scan chains 35-38 can be considered as an external shift register connected in the serial scan chain. Each of the TAP interfaces 25-28 has two basic modes of operation which are selected by toggling the mode select signal rMS from 20 the test bus controller 23. In the first mode, an instruction sequence, including a control bit c and a trigger bit T, the purpose of which will become apparent later, are loaded into the instructions register in the TAP interface. In the second mode, test bus controller 23 shifts serial boundary scan data, 25 i.e. a binary vector, into the scan chain by way of the serial bus segment 30 under the control of the clock signal CLK. The binary vector is then utilized in accordance with the stored instructions .
The precise composition of the binary vector will depend 30 upon the system configuration and the positions at which the faults are to be inserted. The binary vector may be c -~ed by the user and inserted by means of user interface 19. The diagnostic and maintenance software 21, if working correctly, will detect the faults and report them, and/or remedy them, 35 in its usual way, which will not be described in detail here.
In Figure 1, parts of integrated circuit 14, particularly c ~ nts of its "boundary scan" chain 38, are shown in more detail. The boundary scan components comprise a plurality of WO 92/054X8 PCl~CA9l~OOlX9 ~087~g8 scan cells 39, 40, 41 and 42 interposed between ,ULL _l~on~lin~
input/output pads 43, 44, 45 and 46, respectively, alnd core circuitry 47 of the integrated circuit 14. The pads 43 to 46 will be connected to t~rm;n~ (not shown) which will connect 5 the integrated circuit to external, ~-nPntS in the usual way. Within the integrated circuit 14, the scan cells 39 to 42 are connected to the TAP interface Z8 by a control signal bus 48 and a trigger signal bus 49.
In addition, the scan cells 39 to 42 are interconnected 10 between the scan-in and scan-out ports of the TAP i~terface 28, in daisy-chain fashion, by serial scan bus segments 50, 51, 5Z, 53 and 54. (ûther cnnn~n~inn~ are not shown for simplicity of description. ) Although only four scan cells are shown, associated with 15 input pads 43, 44 and output pads 45, 46, it ~ill be understood that there will usually be far more since there will be one scan cell for each input or output pad of the integrated circuit. The input scan cells 39 and 40 are of identical ~ LLu-iLion. The output cells 41 and 42 are of 20 identical construction but differ from the input cellq 39 and 40 in the way in which they are connected to the associated pads and the core circuitry.
Referring now to Figure 2, which shows portions of input scan cell 39 and output scan cell 42 in more detail, input 25 scan cell 39 comprises storage means 55 in the form of D type flip-flop cells 56 and 57, respectively. Serial bus segment 50 connects a "scan-in" port of TAP interface 28 to the input of flip-flop cell 56, the output of which is connected in common to the input of f lip-f lop cell 57 and one inpl1t of a 30 multiplexer 58 which serves as a selector switch. The other input of multiplexer 58 is connected to the control signal bus 48 and the control input of multiplexer 58 is connected to the trigger signal bus 49. The output of multiplexer 58 c~ntrols a second multiplexer 59 which has inputs connected tl~ input 35 pad 43 and the output of flip-flop cell 57, respectively. The output of multiplexer 59 is connected to core circuitry 47 and the output of flip-flop cell 57 is connected to serial scan bus segment 51 to relay the scan signal to the next scan cell , . _ . . , ... . .. . _ . _ _ _ . . . .. .

W0 92/05488 PCT/CA9l/00289 ~087448 8 ~
in the chain. The multiplexers 58 and 59 serve as selectors for selecting either a normal mode of operation, in which the data from input pad 43 passes to the core circuitry 47, or a test mode in which the faulty data in flip-flop 57 is applied 5 to the core circuitry 47.
As mentioned previously, output scan cell 42 is virtually identical in construction to input scan cell 39. Thus output scan cell 42 comprises flip-flop cells 62 and 63 coL~ inlJ
to flip-flop cells 56 and 57, and multiplexers 65 and 66 0 coL~ ng to multiplexers 58 and 59, respectively. These - Ls of output scan cell 42 are interconnected in the same manner as the ~ ULL- -yV~ ;n~ _ ~ Ls of ccan cell 39, but the input and output connections are tr~nCpo6~. Thus, the core circuitrFy 47 is r-nnn~ t~/l to an input of multiplexer 15 66 and output pad 46 is connected to the output of multiplexer 66 .
In operation, when the integrated circuit 14 is functioning normally, test bus controller 23, under the control of miuLv~LVcessor 15, maintains both the digital 20 control signal C and the trigger signal T low. Cunse.luenLly the secondary control signal E applied to multiplexer 59 is low and multiE~lexer 59 routes the data signal from input pad 43 to the core circuitry 47.
When it is desired to test the diagnostic and maintenance 25 software, test bus controller 23 shifts a serial data instruction sequence, using the IEEE 1149.1 protocol, into all of the TAP interfaces 25-28. The instruction sequence enables access to the boundary scan insertion register chain 38. The control bits C and trigger bits T included in this instruction 30 sequence will be set to zero. other bits will serve other functions which need not be r~nci~l~red here. If any of the integrated circuits 11-14 are not to have faults applied to them, the controller 23 -nAc the TAP interfaces of those integrated circuits to bypass them. They do so by connecting 35 the scan-in port to the scan-out port through a bypass register .
Next, and again in accordance with the IEEE protocol, the te6t bus controller 23 shifts the serial buu--d.lL~ register WO 92/0~488 PCr/CA9l/00289 . 2~87448 9 . .
data sequence, i.e. the binary vector, into the scan chains 35-38 of the selected ones of integrated circuits 11-1~. This binary vector is shifted into the chains of scan cells 35-38 by way of the serial scan bus segments 30-34. It shlould be 5 noted that while the instruction sequence and the binary vector are being inserted in this way, the system is operating in its normal manner . The data loaded into f lip-f lop cells 56 and 62, respectively, can be ron~ Pred to be fault insertion "enable" bits. When the "enable" bit is high, it 10 enables a fault to be applied to the associated pad.
Conversely, when the "enable" bit is low there will be no fault applied to the associated pad. The data loaded into flip-flop cell 57 will be the actual fault data value to be applied to the core circuitry 47. Likewise, the data loaded 15 into flip-flop cell 63 will appear as faulty data at output pad 4 6 .
The binary vector is loaded into the scan chain 50 that, in each scan cell which is to apply a fault, flip-flop 62 will hold a logic one value as the "fault enable" bit and flip-flop 20 63 will contain the faulty data to be applied to the output pad. Likewise, in each input scan cell which i5 to apply a fault, flip-flop 56 will hold a logic one as a "fault ~nable"
and flip-flop 57 will hold the faulty data to be applied to the core circuitry.
The test bus controller 23 then shifts a second serial data instruction sequence into the scan chains. This second instruction sequence will assert the trigger signal T in the selected integrated circuits, causing the associated f aulty data to be inserted. Thus, in each input scan cel~ which 30 contains a logic one in its flip-flop 56, multiplexers 58 and 59 will both switch. As a result, the corrP~pn~lin~ output - to the core circuitry 47 will take on the logic value i]~ flip-flop cell 57, regardless of the data which would normally appear at that point. Likewise,in each output scan cell which 35 has a logic one in flop-flop 62, the output pin will assume the logic value in flip-flop 63, regardless of the data which would normally appear at that point.

~087~4~

AP~sllr;n~ that the diagnostic and maintenance software detects the faults and takes appropriate action, the test bus controller 23 then resets the system to its normal op~erating mode by shifting yet another instruction se~uence into the 5 instruction registers of all of the TAP interfaces 25-28 to clear the trigger signal. Alternatively, a TAP reset facility may be invoked.
Trigger signal T may be a signal controlled from the test access interface 28 or it may be applied by way of a separate 10 terminal. Thus, in Figure 2, an OR gate 76 has its output connected to trigger signal bus 49 and one of its two inputs connected to the TAP interf ace 2 8 to receive the trigger signal. The other input of the OR gate 76 is connected to an input pad 67 for application of a separate, external l~rigger 15 signal. It will be appreciated that additional wirillg will be required to provide external access to the input pad 67.
An advantage of such a separate trigger input is that it allows more precise control when simulating intermittent faults, which can be emulated by toggling trigger 6ignal T
2 o high and low .
The invention comprehends various modif ications of the above-described specific e-~o~l;r~nt. For example, scan cell circuits similar to input scan cell 39, but minus flip-flop cell 57 and multiplexer 58, may be included in the scan 25 chain 38, as indicated at 69 in Figure 1, and used to insert faults at arbitrary points within the core circuitry 47. Such a modified scan cell 69 is shown in Figure 3 to comprise a flip-flop 70 connected between serial bus segments 51 and 51', respectively. The output of flip-flop 70 is applied to one 30 input of a multiplexer 71, the other input of which is grounded. The multiplexer 71 is controlled by the trigger signal T by way of the trigger signal bus 49 (see also Figures and 2 ) and has its output connected to one input of an exclusive-oR gate 72. The other input of the exclusive-OR
35 gate 72 is connected into the core circuitry to receive input data and its output is csnnect~d to a point in the core circuitry 47 to which this data would normally be con~eyed.
_ _ _ _ _ _ _ _ _ _ . . . ... ,, . . ,, , ,, .. , . _, . _ . , WO 92/05488 CT/CA9l/00289 208744~
In ef~ect, this inserts exclusive-OR gate 72 into the data path to which a fault i5 to be applied.
In use, the enable bit is stored in flip-flop cell 70 and applied when control signal T is high. Toggling of the 5 multiplexer 71 would selectively inYert the data and apply that as a fault to the core circuitry. Other kinds of faults could be applied by substituting alternative circuitry for exclusive-OR gate 72.
In the described I :'i t, the boundary scan chain 35-10 38 are each twice the length of a conventional boundary scanchain. If preferred, however, the boundary scan flip-flops could be connected in two separate shift register chains, one for the "fault enable" and the other for the "fault data"
- bits. Then flip-flops 56 and 57, for example, would not be 15 in series with each other but rather would be in separate chains .
INDUSTRIAL APPLICABILITY
An advantage of pmh~ i ~ t,s of the present invention is 2 0 that they make use of boundary scan hardware which would be provided for testing hardware. Because the extra l~gic is inserted only in logic paths already devoted to test functions, it does not directly affect normal performance of the integrated circuit.
Another advantage of Pmho~ s of the present invention is that f aults can be applied to selected ones of the integrated circuit's term;nAl pads. Indeed, if deslred, a single fault could be applied.

Claims (34)

CLAIMS:
1. An integrated circuit comprising a test interface, a plurality of terminal pads, a corresponding plurality of scan cells each connected to a respective one of said plurality of terminal pads, and core circuitry, each scan cell comprising an input and an output connected one to a said terminal pad and the other to said core circuitry, storage means and selector means, said storage means of each scan cell being connected, in series with the corresponding storage means of the remainder of said plurality of scan cells, between an input port and an output port of said test interface, said test interface comprising means for loading into the series of storage means a binary vector comprising a series of pairs of binary bits;
each storage means for storing a said pair of binary bits, one of said pair of binary bits comprising a faulty data bit to be applied to said output of said scan cell, the other of said pair of binary bits serving to control application of said one of said pair of binary bits to the output of the scan cell, each selector means being responsive to a control signal, a trigger signal and said other of said pair of bits for selectively connecting either of said input of said scan cell and the output of said storage means to said output of said scan cell, the arrangement being such that application of said faulty data to said scan cell output is dependent upon the state of said other of said pair of bits.
2. An integrated circuit as claimed in claim 1, wherein each said storage means comprises a first storage device connected in series with a second storage device, said second storage device serving to store said faulty data bit and said first storage device serving to store said other of said binary bits .
3. An integrated circuit as claimed in claim 1, wherein said storage means comprises a first storage device and a second storage device connected in series and said selector means comprises a first selector and a second selector, said first selector being operable in response to said trigger signal to apply either of said control signal and the output of said first storage device to control said second selector, said second selector being operable in response to the output of said first selector to select either said input of said scan cell or the output of said second storage device for application of said faulty data bit to said output of said scan cell.
4. An integrated circuit as claimed in claim 1, 2 or 3, wherein said input and said output of said scan cell are connected to an input terminal pad and said core circuitry, respectively, of said integrated circuit.
5. An integrated circuit as claimed in claim 1, 2 or 3 wherein said input and said output of said scan cell are connected to said core circuitry and an input terminal pad, respectively, of said integrated circuit.
6. An integrated circuit as claimed in claim 1, 2 or 3, further comprising OR-gating means having one input connected to said test interface to receive said trigger signal, a second input connected to a test input terminal of said integrated circuit, and an output connected to said selector means .
7. An integrated circuit as claimed in claim 1, further comprising a further storage device in series with said storage means of said scan cells, the output of said further storage device being coupled to one input of a further selector means, said further selector means having a second input grounded, an output connected to circuitry for controlling application of a fault, and a control input coupled to said test interface for reception of said trigger signal .
8. An integrated circuit as claimed in claim 7, wherein said circuitry for controlling application of a fault comprises exclusive-OR gating means having one input connected to the output of said further selector means and its other input and its output connected in series with a data path to which the fault is to be applied.
9. A system comprising at least one integrated circuit, the integrated circuit comprising a test interface, a plurality of terminal pads, a corresponding plurality of scan cells each connected to a respective one of said plurality of terminal pads, and core circuitry, said scan cells each comprising storage means for storing a pair of bits, one of said pair of bits comprising a faulty data bit and the other of said pair of bits comprising an enabling bit; the plurality of storage means being connected in series between a scan input port and a scan output port of said test interface, said test interface being operable to load a binary vector into selected ones of the series-connected storage means, said binary vector comprising a corresponding series of pairs of binar bits, each pair of binary bits comprising, alternately, a said faulty data bit and a said enabling bit, each enabling bit for controlling application of a said faulty data bit by a said scan cell, said system further comprising controller means for controlling said test interface to provide a control signal and a trigger signal, each scan cell further comprising an input and an output connected one to a said terminal pad and the other to said core circuitry, and selector means responsive to said control signal, said trigger signal and said enabling bit for selectively connecting either said input of said scan cell or its said storage means to said output of said scan cell, the arrangement being such that said faulty data bit is applied as the output of said scan cell in dependence upon the state of said enabling bit.
10. A system as claimed in claim 9, wherein said storage means comprises a first storage device connected in series with a second storage device, said second storage device serving to store faulty data bit and said first storage device serving to store said enabling bit.
11. A system as claimed in claim 9, wherein said storage means comprises first and second storage devices connected in series between a scan input and a scan output of said test interface, and said selector means comprises a first selector and a second selector, said first selector being operable to apply either of said control signal and the output of said first storage device to control said second selector, said second selector being operable to select either of said scan cell input and the output of said second storage device for application of said faulty data to said output of said scan cell.
12. A system as claimed in claim 9, 10 or 11, wherein said input and said output of said scan cell are connected to an input terminal pad and said core circuitry, respectively, of said integrated circuit.
13. A system as claimed in claim 9, 10 or 11, wherein said input and said output of said scan cell are connected to said core circuitry and an input terminal pad, respectively, of said integrated circuit.
14. A system as claimed in any one of claim 9, wherein said integrated circuit further comprises OR-gating means having a first input connected to said test interface to receive said trigger signal, a second input connected to an input terminal of said integrated circuit and an output connected to said selector means.
15. A system as claimed in claim 9, 10 or 11, wherein said integrated circuit comprises a further storage device in series with said storage means of said scan cells, the output of said further storage device being coupled to one input of a further selector means, said further selector means having a second input grounded, its output connected to a point in the core circuitry to which a fault is to be applied, and its control input coupled to said test interface for reception of said trigger signal.
16. A system as claimed in claim 15, further comprising exclusive-OR gating means having one input connected to the output of said further selector means and its other input and its output connected in series with a data path to which the fault is to be applied.
17. A system as claimed in claim 9, 10 or 11, further comprising means for diagnosing faults arising from said application of said faulty data bits.
18. A system as claimed in claim 17, wherein said storage means comprises a first storage device connected in series with a second storage device, said second storage device serving to store a said faulty data bit and said first storage device serving to store said enabling bit.
19. A system as claimed in claim 17, wherein said storage means comprises first and second storage devices connected in series between a scan input and a scan output of said test interface, and said selector means comprises a first selector and a second selector, said first selector being operable to apply either of said control signal and the output of said first storage device to control said second selector, said second selector being operable to select either of said scan cell input and the output of said second storage device for application to said output of said scan cell.
20. A system as claimed in claim 17, wherein said input and said output of said scan cell are connected to an input terminal pad and said core circuitry, respectively, of said integrated circuit.
21. A system as claimed in claim 17, wherein said input and said output of said scan cell are connected to said core circuitry and an output terminal pad, respectively, of said integrated circuit.
22. A system as claimed in claim 17, wherein said integrated circuit further comprises OR-gating means having one input connected to said test interface to receive said trigger signal, a second input connected to an input terminal of said integrated circuit and an output connected to said selector means.
23. A system as claimed in claim 17, wherein said integrated circuit comprises a further storage device in series with said storage means of said scan cells, the output of said further storage device being coupled to one input of a further selector means, said further selector means having a second input grounded, its output connected to a point in the core circuitry to which a fault is to be applied, and its control input coupled to said test interface for reception of said trigger signal.
24. A system as claimed in claim 23, further comprising exclusive-OR gating means having one input connected to the output of said further selector means and its other input and its output connected in series with a data path to which the fault is to be applied.
25. A method of testing an integrated circuit comprising a test interface, a plurality of terminal pads, a corresponding plurality of scan cells, and core circuitry, said test interface being operable to load a binary vector comprising a series of pairs of binary bits into said plurality of scan cells, each scan cell comprising an input and an output connected one to a respective one of said plurality of terminal pads and the other to core circuitry of said integrated circuit, storage means in the scan cell for storing a pair of said binary bits of said binary vector, and selector means for selectively connecting either said input of said scan cell or the output of said storage means to said output of said scan cell, the storage means of said plurality of scan cells being connected in series between a scan input port and a scan output port of said test interface, said method comprising the steps of:
(i) loading a binary vector into said series of storage means such that each storage means holds a pair of binary bits, one of the pair of binary bits comprising a faulty data bit and the other of the pair of binary bits comprising an enabling bit, and applying a trigger signal to said selector means to initiate application of said faulty data bit to the output of said scan cell in dependence upon the state of said other bit of said pair of binary.
26. A method as claimed in claim 25, wherein said storage means comprises a first storage device and a second storage device connected in series, and said binary vector is loaded so that said enabling bit is in said first storage device and said faulty data bit is in said second storage device.
27. A method as claimed in claim 26, wherein said selector means comprises a first selector and a second selector, and said step of applying said trigger signal included applying said trigger signal to said first selector, whereby the output of said first selector is applied to said second selector to select the output of said second storage device for application of said faulty data to said output of said scan cell .
28. A method as claimed in claim 25, 26 or 27, wherein said input and said output of said scan cell are connected to an input terminal pad and said core circuitry, respectively, of said integrated circuit.
29. A method as claimed in claim 25, 26 or 27, wherein said input and said output of said scan cell are connected to said core circuitry and an output terminal pad, respectively, of said integrated circuit.
30. A method as claimed in claim 25, 26 or 27, wherein said trigger signal is applied to said selector means by way of said test interface.
31. A method as claimed in claim 25, 26 or 27, wherein said trigger signal is applied to said selector means by way of a separate input terminal of the integrated circuit.
32. A method as claimed in claim 25, 26 or 27, further comprising the step of applying to said test interface, prior to the step of loading said binary vector into said series of storage means, an instruction sequence to control loading of the binary vector into the scan cells, after loading of said binary vector, applying to said test interface a second instruction sequence comprising said trigger signal for initiating application of said faulty data bits and, after application of said faulty data bits, applying a third instruction sequence to said test interface to reset said scan cells to pass data between said terminal pad and said core circuitry.
33. A method as claimed in claim 25, 26 or 27, further comprising the step of monitoring said integrated circuit for faults arising from application of said faulty data bits.
34. A method as claimed in claim 32, further comprising the step of monitoring said integrated circuit for faults arising from application of said faulty data bits before applying said third instruction sequence.
CA002087448A 1990-09-17 1991-08-19 Fault insertion Expired - Fee Related CA2087448C (en)

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US07/583,208 US5130988A (en) 1990-09-17 1990-09-17 Software verification by fault insertion
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Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483518A (en) 1992-06-17 1996-01-09 Texas Instruments Incorporated Addressable shadow port and protocol for serial bus networks
US5576980A (en) * 1991-06-28 1996-11-19 Texas Instruments Incorporated Serializer circuit for loading and shifting out digitized analog signals
JP2770617B2 (en) * 1991-09-05 1998-07-02 日本電気株式会社 Test circuit
US5513188A (en) * 1991-09-10 1996-04-30 Hewlett-Packard Company Enhanced interconnect testing through utilization of board topology data
US5341380A (en) * 1992-03-19 1994-08-23 Nec Corporation Large-scale integrated circuit device
US5640521A (en) * 1992-06-17 1997-06-17 Texas Instruments Incorporated Addressable shadow port and protocol with remote I/O, contol and interrupt ports
FR2693574B1 (en) * 1992-07-08 1994-09-09 Sgs Thomson Microelectronics Method for testing the operation of a specialized integrated circuit, and specialized integrated circuit relating thereto.
JP3563750B2 (en) * 1992-10-16 2004-09-08 テキサス インスツルメンツ インコーポレイテツド Scan-based testing for analog circuits.
EP0642084A1 (en) * 1993-08-04 1995-03-08 Siemens Aktiengesellschaft Testable integrated logic circuit
US5428624A (en) * 1993-10-12 1995-06-27 Storage Technology Corporation Fault injection using boundary scan
US5809036A (en) * 1993-11-29 1998-09-15 Motorola, Inc. Boundary-scan testable system and method
US5600788A (en) * 1994-01-19 1997-02-04 Martin Marietta Corporation Digital test and maintenance architecture
GB2288666B (en) * 1994-04-12 1997-06-25 Advanced Risc Mach Ltd Integrated circuit control
US5642362A (en) * 1994-07-20 1997-06-24 International Business Machines Corporation Scan-based delay tests having enhanced test vector pattern generation
US6243843B1 (en) 1995-01-09 2001-06-05 Agilent Technologies, Inc. Post-mission test method for checking the integrity of a boundary scan test
US5574730A (en) * 1995-01-31 1996-11-12 Unisys Corporation Bussed test access port interface and method for testing and controlling system logic boards
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
US5887001A (en) * 1995-12-13 1999-03-23 Bull Hn Information Systems Inc. Boundary scan architecture analog extension with direct connections
US5668816A (en) * 1996-08-19 1997-09-16 International Business Machines Corporation Method and apparatus for injecting errors into an array built-in self-test
US5938779A (en) * 1997-02-27 1999-08-17 Alcatel Alsthom Compagnie Generale D'electricite Asic control and data retrieval method and apparatus having an internal collateral test interface function
DE69832605T2 (en) * 1997-06-02 2006-08-17 Duaxes Corp. INTERFACE PATTERN AND COMMUNICATION DEVICE USING THIS
NL1006239C2 (en) * 1997-06-05 1998-12-08 Koninkl Kpn Nv Transfer device with an electrical or optical signal bus.
DE19735163A1 (en) * 1997-08-13 1999-03-11 Siemens Ag Integrated electronic component with hardware fault input for testing
WO1999023503A1 (en) * 1997-10-31 1999-05-14 Koninklijke Philips Electronics N.V. Core test control
US6092226A (en) * 1998-02-10 2000-07-18 Cray Research, Inc. Fabrication of test logic for level sensitive scan on a circuit
US6408413B1 (en) * 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6405335B1 (en) * 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US6327676B1 (en) * 1998-03-31 2001-12-04 Emc Corporation Test equipment
US6536008B1 (en) 1998-10-27 2003-03-18 Logic Vision, Inc. Fault insertion method, boundary scan cells, and integrated circuit for use therewith
US6499124B1 (en) * 1999-05-06 2002-12-24 Xilinx, Inc. Intest security circuit for boundary-scan architecture
DE19961148C1 (en) * 1999-12-17 2001-09-06 Siemens Ag Integrated electronic module for influencing external functions
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US7174492B1 (en) 2001-04-12 2007-02-06 Cisco Technology, Inc. AC coupled line testing using boundary scan test methodology
US6804801B2 (en) * 2001-06-25 2004-10-12 Lucent Technologies Inc. Integrated circuit fault insertion system
DE10204885A1 (en) * 2002-02-06 2003-08-14 Siemens Ag Testing of ASIC type circuits using design for test methods by use of a mode control cell that allows individual switching of component inputs and outputs both in normal and test modes
US7284159B2 (en) * 2003-08-26 2007-10-16 Lucent Technologies Inc. Fault injection method and system
US7340661B2 (en) * 2003-09-25 2008-03-04 Hitachi Global Storage Technologies Netherlands B.V. Computer program product for performing testing of a simulated storage device within a testing simulation environment
US7165201B2 (en) * 2003-09-25 2007-01-16 Hitachi Global Storage Technologies Netherlands B.V. Method for performing testing of a simulated storage device within a testing simulation environment
DE60314525T2 (en) 2003-12-17 2008-02-28 Stmicroelectronics Ltd., Almondsbury TAP time multiplexing with sampling test
US7650542B2 (en) * 2004-12-16 2010-01-19 Broadcom Corporation Method and system of using a single EJTAG interface for multiple tap controllers
US7657807B1 (en) * 2005-06-27 2010-02-02 Sun Microsystems, Inc. Integrated circuit with embedded test functionality
US7747901B2 (en) * 2005-07-20 2010-06-29 Texas Instruments Incorporated Auxiliary link control commands
US7689866B2 (en) * 2006-10-18 2010-03-30 Alcatel-Lucent Usa Inc. Method and apparatus for injecting transient hardware faults for software testing
CN100547562C (en) * 2006-10-18 2009-10-07 国际商业机器公司 The method and system of the unit testing use-case of problem when generation can be reproduced operation automatically
WO2009013674A1 (en) * 2007-07-20 2009-01-29 Nxp B.V. Automatic address assignment for communication bus
US8073996B2 (en) * 2008-01-09 2011-12-06 Synopsys, Inc. Programmable modular circuit for testing and controlling a system-on-a-chip integrated circuit, and applications thereof
US20110010596A1 (en) * 2009-07-09 2011-01-13 Tao-Yen Yang Testable circuit with input/output cell for standard cell library
US8615693B2 (en) * 2011-08-31 2013-12-24 Lsi Corporation Scan test circuitry comprising scan cells with multiple scan inputs

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4669081A (en) * 1986-02-04 1987-05-26 Raytheon Company LSI fault insertion
US4875209A (en) * 1988-04-04 1989-10-17 Raytheon Company Transient and intermittent fault insertion
DE68928613T2 (en) * 1988-09-07 1998-09-24 Texas Instruments Inc Bidirectional boundary scan test cell
JPH02181677A (en) * 1989-01-06 1990-07-16 Sharp Corp Test mode switching system for lsi

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JP2628105B2 (en) 1997-07-09
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EP0549602B1 (en) 1995-02-15
US5130988A (en) 1992-07-14

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