CA1292550C - Epitaxial gallium arsenide semiconductor wafer and method of producing the same - Google Patents

Epitaxial gallium arsenide semiconductor wafer and method of producing the same

Info

Publication number
CA1292550C
CA1292550C CA000517386A CA517386A CA1292550C CA 1292550 C CA1292550 C CA 1292550C CA 000517386 A CA000517386 A CA 000517386A CA 517386 A CA517386 A CA 517386A CA 1292550 C CA1292550 C CA 1292550C
Authority
CA
Canada
Prior art keywords
layer
gaas
substrate
gap
gaasp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CA000517386A
Other languages
French (fr)
Inventor
Masayoshi Umeno
Shiro Sakai
Shinichiro Yahagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Daido Steel Co Ltd
Nagoya Institute of Technology NUC
Original Assignee
Daido Steel Co Ltd
Nagoya Institute of Technology NUC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP19563085A external-priority patent/JPS6258616A/en
Priority claimed from JP19562885A external-priority patent/JPS6258614A/en
Priority claimed from JP19562985A external-priority patent/JPS6258615A/en
Priority claimed from JP60195435A external-priority patent/JPS6258690A/en
Application filed by Daido Steel Co Ltd, Nagoya Institute of Technology NUC filed Critical Daido Steel Co Ltd
Priority to CA000616160A priority Critical patent/CA1322040C/en
Application granted granted Critical
Publication of CA1292550C publication Critical patent/CA1292550C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0693—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02461—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
    • H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/901—Levitation, reduced gravity, microgravity, space
    • Y10S117/902—Specified orientation, shape, crystallography, or size of seed or substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/072—Heterojunctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/097—Lattice strain and defects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/16—Superlattice
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

Abstract

ABSTRACT OF THE DISCLOSURE

A semiconductor wafer having an epitaxial GaAs layer, including a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5° and 5° with respect to (100); and at least one intermediate layer epitaxially grown on the major surface of the monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between the Si substrate and the epitaxial GaAs layer which is epitaxially grown on a major surface of a top layer of the at least one intermediate layer. The at least one intermediate layer may comprise a GaP layer or one or more GaP/GaAsP, GaAsP/GaAs superlattice layers. The wafer may be used to produce a semiconductor light emitting element which has a plurality of crystalline GaAs layers including a light emitting layer epitaxially grown on the GaAs layer on the intermediate layer. The wafer may also be used to produce a compound semiconductor device such as amplifying and switching elements, light emitting and receiving elements and photovolataic elements.
Methods for producing the semiconductor wafer, light emitting element and compound semiconductor devices are also disclosed.

Description

;9Z~51~

TITLE OF THE INVENTION
FPITAXIAL GALLI~M ARS~NIDE SEMICO~DUCTOR WAFER

AND MFTUOD OF PRODUCING T~ SAME

BACKGROUND OF THE INVENTION

Field of the Invention The present invention relates to semiconductor wafers having an epitaxially grown gallium arsenide layer, useful for fabricating various GaAs compound semiconducting devices, and methods suitable for producing such semiconductor wafers and devices.
Discussion of the Related Art Group III-V compound semiconductors with a gallium arsenide (GaAs) layer have high carrier mobility, direct-gap band structure, and variable nature of band gap and lattice parameter or constant in the case of the compounds consisting of three or four elements. Owing to these characteristics, the Group III-V compound semiconductors have been enjoying expanding industrial " appllcations for fabricating not only a variety of semiconductor elements such as high-speed transistors, laser ~ diodes, light emitting diodes (LED~, phototransistors, photodiodes and solar cells, but also integrated circuits incorporating these semiconductor .
elements. An active layer providing such an active element is~ formed in a monocrystalline substrate of gallium arsenide, by preferential diffusion or ion implantation . ~
.

, ~ - ' , ~

`- lZ~?Z~50 technique, or alternatively as an epitaxial GaAs layer formed by epitaxy on the GaAs substrate crystal.
However, a monocrystalline gallium arsenide (GaAs) substrate suffers from some disadvantages over a monocrystalline silicon (Si) substrate, e.g., more difficulty in obtaining an ingot of a relatively large diameter, higher cost of production, and lower mechanical strength. In the light of these disadvatages of the monocrystalline gallium arsenide substrate, there has been an attempt to use a monocrystalline substrate of silicon, since the technologies for producing and processing its ingot are most advanced in the field of semiconductor materials. In this case, an active layer of gallium arsenide is epitaxially grown or formed by epitaxy on the surface of the ~onocrystalline silicon substrate. However, the thus obtained semiconductor wafer tends to have a lattice mismatch or dislocation of the epitaxial gallium arsenide active layer and the silicon substrate, and is not satisfactory in crystallinity of the active layer.

SUMMARY OF THE INVENTION
It is therefore a primary object ~of the present invention to provide a semiconductor wafer having a gallium arsenide layer of excellent crystallinity formed by epitaxy on a monocrystalline silicon substrate, suitable for economical, efficient large-scale production of gallium arsenide semiconductor elements or devices including newly .. ' . ' developed optical IC arrangements.
In an effort to an improved semiconductor wafer with a gallium arsenide layer epitaxially grown on a major surface of a monocrystalline silicon substrate, the present inventors have conducted extensive studies and investigations on an intermediate buffer layer to be interposed between the silicon substrate and the epitaxial gallium arsenide layer for accommodating a lattice mismatch therebetween, and on an off angle at which the major surface of the silicon substrate is inclined with respect to a given plane (lO0) of the crystal.
The studies and investigations revealed that the crystallinity of an epitaxially grown gallium arsenide layer was enhanced if the major surface of the monocrystalline silicon substrate was inclined to (lO0) at an angle within a selected optimum range. Further, it was found that the crystallinity of the gallium arsenide layer was improved with selected materials of the intermediate layer, or where the intermediate layer includes a superlattice layer or layers of a selected combination or combinations of materials.
In the meantime, the inventors' studies and investigations indicated an improvement in the crystallinity of the epitaxial gallium arsenide layer, where the intermediate buffer layer consists of a plurality of layers including a layer of gallium phosphide (GaP), at least one gallium phosphide/gallium arsenide-phosphide , lZ~ V

(GaP/GaAsP) superlattice layer, and at least one yallium arsenide-phosphide/gallium arsenide (GaAsP/GaAs) superlattice layer, such tha~ the GaP layer and the GaP/GaAsP and GaAsP/GaAs superlattice layers are super-posed on each other in the order of description as seenin the direction from the major surface of the silicon substrate. The inventors also recognized a further improvement in the crystallinity of the epitaxial gallium arsenide layer where the off angle of the major surface of the silicon substrate relative to (100) is held within a given range.
The present invention was developed as a result of the above findings of the inventors.
According to a first aspect of the invention, there is provided a semiconductor wafer having an epitaxial GaAs layer, comprising:
- a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5 and 5 with respect to (100); and an intermediate layer epitaxially grown on said major surface of said monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between said Si substrate and said epitaxial GaAs layer, the GaAs layer being epltaxially grown on a major surface of a top layer of 5 said intermediate layer, wherein said intermediate layer is selected from (a) a single GaP layer, and 9;~S~O

(b) a GaP layer formed on said Si substrate; at least one GaP/GaAsP superlattice layer formed on said GaP layer;
and at least one GaAsP/GaAs superlattice layer on said at least one GaP/GaAsP superlattice layer, said epitaxial GaAs layer being formed on said at least one GaAsP/GaAs superlattice layer.
In accordance with a second aspect of the invention there is provided, a method of producing a semiconductor wafer having an epitaxial GaAs layer comprising the steps of:
preparing a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5 and 5 with respect to (100);
forming a GaP layer by expitaxy on a major surface of said monocrystalline Si substrate;
- forming at least one GaP/GaAsP superlattice layer by epitaxy on said GaP layer;
forming at least one GaAsP/GaAs superlattice layer by epitaxy on said at least one GaP/GaAsP superlattice layer;
and forming a GaAs layer by epitaxy on said at least one GaAsP/GaAs superlattice.
In accordance with a third aspect of the invention there is provided, a semiconductor light emitting element havlng an epitaxial GaAs layer, compFising:

.
'J

a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5 and 5 with respect to (100), an intermediate layer epitaxially grown on a major surface of said monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between said Si substrate and said epitaxial GaAs layer, said epitaxial GaAs layer being epitaxially grown on a major surface of a top layer of said intermediate layer, wherein said intermediate layer is selected from (a) a GaP layer and, (b) a GaP layer formed on said Si substrate; at least one GaP/GaAsP superlattice layer formed on said GaP layer;
and at least one GaAsP/GaAs superlattice layer formed on said at least one GaP/GaAsP superlattice layer, said epitaxial GaAs layer being formed on said at least one GaAsP/GaAs superlattice layer; and a plurality of semiconductor crystalline layers containing GaAs as base elements which are epitaxially grown on said epitaxial GaAs layer and superposed on each other, said crystalline layers including a light emitting layer.
In accordance with a fourth aspect of the invention there is provided, a compound semiconductor ; device having an epitaxial GaAs layer, comprising:
a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5 and S~ with ` respect to (100);

- ~Lz~s~

an intermediate layer epitaxially grown on said major surface of said monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between said Si substrate and said epitaxial GaAs layer, the GaAs layer being epitaxially grown on a major surface of a top layer of said at least one ~ntermediate layer, wherein said intermediate layer is selected from (a) a GaP layer and ~ b) a GaP layer formed on said Si substrate; at least one GaP/GaAsP superlattice layer formed on said GaP layer;
and at least one GaAsP/GaAs superlattice la~er formed on said at least one GaP/GaAsP superlattice layer, said epitaxial GaAs layer being formed on said at least one GaAsP/GaAs superlattice layer; and at least one semiconductor element formed on said epitaxial GaAs layer.
The crystallinity of the epitaxial gallium arsenide (GaAs) layer formed on the silicon (Si) substrate was evaluated by measuring the surface roughness of the GaAs layer by a contact-type surface roughness tester, and the value (meV) of photo-luminescence full-width at half maximum. The specified optimum range (0.5 to 5 degrees) of the off angle of the Si substrate permits the epitaxial GaAs layer embodying the invention to have a higher degree of crystallinity, and a smaller, than those of a GaAs layer to be grown on the Si substrate of (100) orientation (commonly used as -' "

, .

lZ~ZSSC~ .
-- 8 _ a major surface on which the GaAs layer is formed). The off angle range is preferably between 1 and 3, and more preferably in the neighborhood of 2.
The novel epitaxially grown gallium arsenide layer is given an enhanced level of crystallinity, thanks to the selected off angle range between 0.5 and 5 of the Si substrate to (100), and to the provision of at least one intermediate buffer layer which is formed by epitaxy on the major surface of the Si substrate, and on which the gallium arsenide layer is formed by epitaxy. Accordingly, the economical large-scale production of semiconductor wafers is permitted using a silicon substrate and a gallium arsenide active layer, which are suitable for fabricating various high-performance semiconductor elements, integrated circuits,and semiconductor devices such as optical integrated circuits, and other hybrid integrated circuits which are combinations oP conventional silicon ICs and Ground III-V compound gallium arsenide semiconductor ICs.
According to one advantageous feature, the at least one intermediate layer consists of a single gallium phosphide (GaP) layer. Alternatively, the at least one intermediate layer may include at least one superlattice layer.
According to another advantageous feature, the at least one intermediate layer consists of at least one GaP/GaAsP superlattice layer formed on the Si substrate, ,J

12~2S50 9 _ and at least one GaAsP/GaAs superlattice layer which is formed on the at least one GaP/GaAsP superlattice layer and on which the epitaxial GaAs layer is formed.
According to a further advantageous feature, there is formed a single GaP layer, or there are formed an aluminum phosphide (AlP) layer and an aluminum-gallium phosphide (AlGaP) layer, between the Si substrate and the above-indicated at least one GaP/~aAsP superlattice layer.
In the semiconductor wafer, where the second GaAs layer is formed on the intermediate buffer layers which consist of the GaP layer, the GaP/GaAsP and GaAsP/GaAs superlattice layers, all of these intermediate layers are superposed on each other in the order of description as seen in the direction from the major surface of the Si substrate. The provision of these intermediate layers contribute to improved crystallinity of the epitaxial GaAs layer formed on top of the intermediate layers. Therefore, this semiconductor wafer using a silicon substrate and an epitaxial gallium arsenide active layer is suitably applied for the fabrication of various high-quality semiconductor elements ! integrated circuits, and optical integrated circuits and other hybrid integrated circuits which are combinations of conventional silicon ICs and Ground III-V compound gallium arsenide ICs. For example, the semiconductor wafer is used for bi-polar transistors, field effect ' -`` lZ~?2S50 - 9a -transistors, light emitting diodes, laser diodes, light receiving elements, solar cells, and other semiconductor elements, and is furt~er used for integrated circuits incorporating such semiconductor elements in combination.
Embodiments of the invention will now be described with reference to the accompanying drawings, in which:
Fig. 1 is a cross sectional view of a semiconductor wafer embodying the principle of the present invention;
Fig. 2 is a graphical representation of measurements indicating the surface roughness of an epitaxial GaAs layer of the wafer versus the off angle of a Si substrate of the wafer:
Fig. 3 is a cross sectional view of another semiconductor wafer embodying the invention;
Fig. 4 is a graphical representation of measurements indicating the value (meV) of photoluminescence full-width at half maximum of an epitaxial GaAs layer of the wafer of Fig. 3 versus the off angle of a Si substrate of the wafer;
Fig. 5 is a cross sectional Vi8W of a further semiconductor wafer embodying the invention;
Fig. 6 is a cross sectional view of a still further embodiment of the invention in the form of a laser diode;

:~ I

``lZgZS50 - 9b -Fig. 7 is a graph showing an input-output characteristic curve of the laser diode of Fig. 6;
Fig. 8 is a graph showing a spectrum of a laser beam produced by the laser diode;
5Fig. 9 is a cross sectional view of yet another embodiment of the invention in the form of a photodiode;
Fig. 10 is a graph showing the quantum efficiency .

:
:

: ~ ' :, , : : :
~ : ~
;
. :

:
.
~ J ~ :

: , .
, 1~92S50 versus wavelength of a light beam emitted by the photodiode of Fig. 9;
Fig. 11 is a cross sec~ional view of a further embodiment of the invention in the form of a solar cell; and Fig. 12 is a graph showing spectral sensitivity curves of the solar cell of Fig. 11.

DESCRIPTION OF THE PREFERRED EMBODIMENTS
The following examples are given for illustrative purpose only, to further clarify the principle of the present invention, referring to the accompanying drawings.
Example 1 Referring first to Fig. 1, there is shown in cross section one inventive embodiment of a semiconductor wafer. In the figure, reference numeral 10 designates an n-type monocrystalline silicon (Si) substrate. On this Si substrate are formed an intermediate gallium phosphide (GaP) layer 30 and an epitaxial gallium arsenide (GaAs) layer 50. The monocrystalline Si substrate 10 has a thickness of 300 microns.
20 The GaP layer 30 is 0.5 micron thick, while the GaAs layer 50 is
2 microns thick. The GaP and GaAs layers 30, 50 were formed continuously by epitaxy on the Si substrate, in a metalorganic chemical vapor deposition process ~MOCVD), in a reaction furnace in the form of a horizontal induction-heating furnace under the atmospheric pressure. As the materials for the GaP and ,.

. , . :
- "` ' ,:
.

- ~z~z~so GaAs layers 30, 50, trimethylgallium (TMGa, Ga(Ch3)3), arsine (AsH3) and phosphine (PH3) were used. The flow rates of these gases were controlled accurately by a flow control device so that the epitaxial growth of the GaP and GaAs layers may occur at a suitable rate. No pre-cracking of the Group V elements was effected. Prior to starting the epitaxy, the Si substrate 10 was first annealed at 1000C
in hydrogen for ten minutes, to remove an oxide layer from its surface. Subsequently, the Si substrate 10 was maintained at 900C to permit an epitaxial growth of GaP
into the intermediate GaP layer 30, and thereafter maintained at 650C to allow an epitaxial growth of GaAs into the GaAs layer 50.
In the above-described manner, a number of semiconductor wafers were prepared, with different off angles to (100) of the major surface 11 of their Si substrates 10.
The roughness of an exposed surface 51 of the epitaxial GaAs layer 50 of each wafer was measured by a contact type surface roughness testerO The measurements of the individual wafers are shown in Fig. 2, wherein the off angle ~ (degree) of the major surface 11 of the Si substrate 10 to (100) is taken along the abscissa, while the peak-to-peak roughness (Angstrom) of the surface 51 of the GaAs layer is taken along the ordinate. As is apparent from the graph in Fig. 2, the smoothness of the surface 51 of the wafers with the substrate off angle within a range between 0.5 to 5 is improved over that with the substrate ~ , ~ .

SS~) off angle of 0. The best result is obtained with the off angle range from 1 to 2, within which the roughness of the surface 51 is less than 50 Angstroms, more than three kimes as small as 150 Angstroms in the case oE the off angle of 0.
Example 2 Referring next to Fig. 3, there is shown in cross section another example of a semiconductor wafer wherein reference numeral 10 designates an n-type monocrystalline Si substrate on which a plurality of intermediate layers 30 ar~
formed, so as to accommodate a latti~e mismatch between the Si substrate 10 and an epitaxial GaAs layer 50 formed on the intermediate layers 30. This Example 2 is different from Example 1 in that the four intermediate layers 30 are used in Example 2, in place of the single intermediate GaP layer 30 used in Example 1. Described more specifically, the intermediate layers 30 of Example 2 consist of: a first intermediate layer in the form of an aluminum phosphide (AlP) layer 31 which is easily epitaxially grown on the Si substrate 10, with a high degree of adherence thereto; a second intermediate layer in the form of an aluminum gallium phosphide (Alo 5GaO 5P) layer 32 formed on the first intermediate AlP layer 31:
a third intermediate layer in the form of ten superlattice layers 33 of gallium phosphide ~GaP) and gallium arsenide-phosphide (GaAsO 5Po 5), formed on the second intermediate Alo 5GaO 5P layer 32; and a i~

~ - 13 - lZ9Z55~
fourth intermediate layer in the form of ten suerlattice layers 34 of gallium arsenide (GaAsO 5Po 5) and gallium arsenide (GaAs), formed on the third intermediate GaP/GaAsO 5P0 5 superlattice layer 33. The Si substrate 10 is 300 microns thick, and the epitaxial GaP layer 50 is 2 microns thick. The four intermediate layers 30 have a total thickness of 0.42 micron. Each of the first and second intermediate layers 31, 32 is 100 Angstroms thick. Each of the ten third intermediate GaP/GaAsO 5P0 5 superlattice layers 33, and each of the ten fourth intermediate GaAsO 5P0 5/GaAs superlattice layers 34 have a thickness of 200 Angstroms.
As in Example 1, a metalorganic chemical vapor deposition process (MOCVD) was employed to form the intermediate layers 30 and the GaAs layer 50. In addition to the materials used in Example 1, trimethylaluminum (TMAl.Al(CH3)3) was used. The temperature during the epitaxial growth of the first through fourth intermediate layers 31-34 was 830~C, and the temperature during the epitaxial growth of the GaAs layer 50 was 730C. The other conditions were the same as in Example 1.
In the above-indicated manner, a number of semiconductor wafers were prepared, with different off angles to (100) of the major surface 11 of their Si substrates 10.
The photoluminescense full-width at half maximum (meV) was measured for each wafer prepared. The - 14 - lZ92~SO
measurements of the individual wafers are shown in Fig. 4.
As indicated in the figure, the meV value is lower with the substrate off angle within a range between 0.5 to 5, than that with the substate off angle of O. This means improved crystallinity of the epitaxial GaAs layer 50 of the present wafers. Comparatively good results were obtained with the Si substrates 10 having an off angle within a range from 1 to 4, and the best results were obtained with the Si substrate 10 with an off angle in the neightborhood of 2 .
Example 3 Semiconductor wafers were prepared according to Example 2 of Fig. 3, but without the first and second intermediate layers 31 and 32. Photoluminescense tests conducted on these wafers showed substantially the same results as in Example 2. That is, the tests revealed improvement in the crystallinity of the epitaxial GaAs layer 50 where the off angle of the Si substrate 10 is within the range between 0.5 and 5.
Example 4 In ~Example 4, the first and second intermediate layers 31 and 32 of the wafer of Flg. 3 were replaced by a single GaP layer having a thickness of 0.5 micron.
Photoluminescense tests showed similar results, i.e., - improved crystalIinlty of the GaAs layer 50 on the wafers whose Si substrates 50~have an~off angle between 0.5 and 5, .
.

lZ~ZSS(3 Example 5 This example was given to manifest that the crystallinity of the epitaxial GaAs layer 50 may be improved even when the off angle of the Si substrate 10 is o.
A wafer prepared according to Example 5 is depictod in Fig. 5. The wafer include~ a plurality of intermediate layers 30 to accommodate a lattice mi~match between an n-type monocrystalline (100)-oriented Si substrate 10 (with an off angle of 0) and an epitaxial GaAs layer 50. The intermediate layers 30 consist of: a first intermediate layer in the form of a GaP layer formed on the Si substrate 10; a second intermediate layer in the form of ten superlattice layers 32 of gallium phosphide (GaP) and gallium arsenide-phosphide (GaAsO 5Po 5), formed on the GaP layer 31; and a third intermediate layer in the form of ten superlattice layers 33 of gallium arsenide (GaAs~ 5Po 5) and gallium arsenide (GaAs), formed on the second intermediate GaP/GaAsO 5Po 5 superlattice layer 33. The Si substrate 10 is 300 microns thick, and the epitaxial GaP layer 50 is 2 microns thick. The three intermediate layers 30 (31, 32, 33) have a total thickness of 0.9 micron. The first intermediate layer 31 is 0.5 micron thick. Each of the ten second intermediate GaP/GaAsO 5Po 5 auperlattice layers 32, and each of the ten third intermediate GaAsO 5Po 5/GaAs superlattice layers 33 have a thickness of 200 Angstroms.
The intermediate layers 30 and the epitaxial GaAs ~".

' ~.

~2~?ZS50 layers were formed continuously by epitaxy on the Si substrate 10, in a metaloranic chemcal vapor deposition process (MOCVD), within a horizontal induction-heating furnace under the atmospheric pressure. As the materials 5 for the vapor deposition, trimethylgallium (TMGa, Ga(Ch3)3), arsine (AsH3) and phosphine (PH3) were employed.
The overall flow rate of these gases was 2.5 liters/min., and the flow rate of each individual gas was controlled accurately by a flow control device so as to achieve an 10 epitaxial growth rate of 0.1 micron/min. No pre-cracking of the Group V elements was effected. Prior to starting the epitaxy, the Si substrate 10 was first annealed at 950 C
with a flow of PH3 at lOOcc/min. Thereafter, the Si substrate 10 was maintained at 900C to permit an epitaxial 15 growth of GaP into the first intermediate GaP layer 31, and then at 830C to allow epitaxial growth of the second and third intermedlate superlattice layers 32, 33.
Subsequently, the epitaxial growth temperature was lowered down to 650C, to grow the GaAs layer~ 50 on the r20 GaAsO 5Po 5/GaAs superlattice layer 33. The annealing temperature of the Si substrate 10 may be selected within a range from 600 C to 1100C, and the annealing period during which the Si substrate lO is exposed to PH3 may be selected within a range from 1 to 60 minutes.
In the above-described manner, the semiconductor wafer of Flg. 5 (Sample No. ~1) was prepared, and its photoluminescense characteristic was compared with those of , , - 17 - ~2~Z550 Comparative Samples Nos. 2-4. The measured photoluminescense full-width at half maximum (meV) at 150K
are indicated in the following table.

-Samples Composition PL Full-width at 5 _ half maximum (meV) No. l GaAs/(GaAsP/GaAs)/ 45 (Example 5) (GaP/GaAsP)/GaP/Si No. 2 GaAs/(GaAsP/GaAs)/ 52 (GaP/GaAsP)/Si 10 No. 3 GaAs/Ge/Si 62 No. 4 GaAs/GaAs 33 ~`
It will be understood from the above table that Comparatlve Sample No. 3 using a single intermediate layer of Ge had the largest measurement of 62 meV, and that the second largent measurement (52 meV) was obtained on Comparative Sample No. 2 which uses GaP/GaAsO 5Po 5 superlattice layers and GaAsO.5PO.5/GaAs superlattice layers. Sample No. l of the present Example 5 had a value of 45 meV. This value lS considered to indicate a relatively high degree of crystallinity of the GaAs layer 50 of Sample No. l, in view of the fact that Comparative Sample No. 4 which uses a GaAs substrate for an epitaxial GaAs layer had a value of 33 meV.
Example 6 Referring next to Fig. 6, there is shown another .
,~

,.~ . .
` '' - l8 - ~Z9z~5v embodiment of the present invention in the form of a semiconductor laser diode. In the figure, reference numeral l0 designates an n-type monocrystalline Si substrate having a major surface which is inclined a~ 2 with respect to the (l00) orientation, Reference numeral 30 generally indicates a plurality of intermediate layers, while reference numeral 50 indicates an n-type epitaxially grown GaAs layer. On the epitaxial GaAs layer 50, the following layers are superposed on each other in the order of description:
n-GaO 7Alo 3As cladding layer 52; i-GaAs active layer 54;
p-GaO 7Alo 3As cladding layer 56; P-GaAs cap layer 58; sio2 insulating layer 60; and Au-Zn electrode 62 (anode). An Au-Sn electrode 64 (cathode) is also formed on the epitaxial n-GaAs layer 50. The thicknesses of the layers l0, 30, 50, 52, 54, 56 and 58 are as follows:
Si substrate l0: 300 microns Intermediate layers 30: 0.25 micron (total) GaAs layer 50: 2 microns Cladding layer 52: l.5 microns 20 Active layer 54: 0.l micron Cladding layer 56; l.5 microns Cap layer~58: 0.5 micron The intermediate layers 30 consist of: a first intermediate layer in the form of a single GaP layer 31 formed on the Si substrate l0; a second intermediate layer in the form of five Gap/GaAsO 5Po 5 superlattice layers 32 formed on the GaP layer 31; and a third intermediate layer ~' ' : ' ' l~Z~50 in the form of five GaAsO 5Po 5/GaAs superlattice layers 33 formed on the second intermediate layer 32. The first intermediate GaP layer 31 has a thickness of 500 Angstroms, and each superlattice layer of the second and third intermediate layers 32, 33 has a thickness of 200 Angstroms The layers 30, 50, 52, 54, 56 and 58 were formed continuously on each other by epitaxy on the Si substrate 10, in a metaloranic chemcal vapor deposition process (MOCVD), in a horizontal induction-heating furnace under the atmospheric pressure. As the materials far the vapor deposition, trimethylgallium (TMGa, ( 3 3 ' trimethylaluminum (TMAl.Al(CH3)3), arsine (AsH3) and phosphine (PH3) were employed. As p-type and n-type dopants, dietylzinc (DEZn) and hydrogen serenide (H2Se) were used. The flow rates of these gases were controlled accurately by a flow control device so as to achieve a suitable rate of epitaxial growth of crystals. No pre-cracking of the Group V elements was effected. Prior to starting the epitaxy, the Si substrate 10 was first r~ annealed at 950C with a flow of PH3 at lOOcc/min., to remove the oxide layer from its surface. Thereafter, the Si substrate 10 was maintained at 900C to permit an epitaxial growth of a GaP crystal into the first intermediate GaP
layer 31, and then at 700C to allow epitaxial growth of the second and third intermed~iate superlattice layers 32, 33. The epitaxial growth temperature of 700 was further 9~S50 maintained to grow the n-GaAs y , 0 7 0.3 cladding layer 52, GaAs active layer 54, p-GaO 7Alo 3AS
cladding layer 56 and p-GaAs cap layer 58. Subsequently, the surface of the p-GaAs cap layer 58 was coated with a photoresist or light-sensitive coating. A selected area of the applied photoresist coatlng was covered with a mask, and the non-covered area of the photoresist coating was exposed to light, to provide a mask for a subsequent etching process. The portions of the layers 52, 54, 56, 58 corresponding to the exposed area of the photoresist were removed in the etching process, whereby a portion of the surface of the n-GaAs layer 50 was exposed, as shown in Fig. 6. Then, Sio2 was applied to the surface of the p-GaAs cap layer 58, to form the sio2 insulating layer 60. A
recess was formed in the insulatlng layer 60 in a known photolithographic mannerj and the Au-Zn electrode 62 (anode) was formed by vapor deposition on the insulating layer 60. Similarly, the Au-Zn electrode 64 (cathode) was formed by vapor deposition and diffusion on the exposed surface of the n-GaAs layer. The thus prepared multilayered structure was cut into a plurality of laser diodes, such that each diode had a laser emitting face The laser diodes were activated to produce a lasing action. The input-output characteristic curve is shown in Fig. 7. The threshold value of current was 460 mA.
The spectrum of the emitted light is given in Fig. 8.

.

.

-- 21 - ~Z~?zSSO
Example 7 Referring further to Fig. 9, there is shown a further embodiment of the present invention in the form of a photodiode. In the figure, reference numeral 13 indicates an n-type monocrystalline Si substrate having a major surface which is inclined at 2 with respect to (100). On this Si substrate 13, there are formed an intermediate n Gap layer 34, an epitaxial n GaAs layer 70, an epitaxial n GaAs layer 71, and an epitaxial p-GaAs layer 72. A Au-2n electrode 73 and a Au-Sn electrode 74 are formed on the top surface of the p-GaAs layer 72 and the bottom surface of the Si substrate 13, respectively. The layers 70, 71 and 72 constitute a PIN diode The Si substrate 13 which has an initial thickness of 300 microns, was ground to 50 microns 15 after the layers 34, 70-72 had been formed thereon by epitaxy. Thicknesses of the epitaxially grown layers 34, 71, 72 and 73 are 1 micron, 0.5 micron, 2.5 microns and 0.5 micron, respectively. These layers were formed in an MOCVD
process as practiced in the preceding Examples. The 20 intermediate layer 34 was grown at 900C, and the layers 71-73 were grown at 650C. After these layers were formed by epitaxy, the electrodes 73, 74 were vapor deposited, and the prepared multilayered structure was cut into a plurality of photodiodes, such that each photodiode had a light receiving face. The quantum efficiency (emitted energy/incident energy) of the thus produced photodiodes, in relation to the wavelength, is shown in Fig. 10.

- 22 - lZ925SO
Example 8 Referring next to Fig. 11, there is illustrated yet another embodiment of the invention in the form of a solar cell. In the figure, reference numeral 12 designates an n-type monocrystalline Si substrate having a major surface which is inclined at 2 to (100). On this Si substrate 12, there are epitaxially formed the following epitaxial layers: a first intermediate GaP layer 35; a second intermediate layer in the form of GaP/GaAsO 5Po 5 superlattice layers 36; a third intermediate layer in the form of GaAsO 5Po 5/GaAs superlattice layers 37; an n-GaAs layer 80; a p-GaAs layer 81; and p-GaO 2Alo 8As layer 82-Reference numeral 84 designates a non-reflection sio2 coating, and numerals 85 and 86 indicate Au-Zn and Al electrodes, respectively. The Si substrate 12 which has an initial thickness of 300 microns, was ground to 50 microns after the intermediate layers 35-37 and the layers 80-82, 84 had been epitaxially grown thereon. The first intermediate GaP layer 35 is 500 Angstroms thick. The 20 thicknesses of the layers 80, 81, 82 and 84 are 0.5 micron, 0.5 micron, 0.1 micron and 80 nanometers, respectively.
These epitaxial layers 35-37, 80-82 were formed in a metalorganic chemical vapor deposition process (MOCVD) as in the preceding Examples. The growth temperature was 900 C
25 for the intermediate layer 35, and 650 C for the layers 80-82. After the layer 82 had been formed, SiO2 was applied by sputtering to form the non reflection coating 84 on the --~ lZ~2~0 layer 82. By photolithogray and etching techniques, recesses were formed in the selected areas of the coating 84 and the layer 82, in order to accommodate the Au-Zn electrodes 85 which wére formed by vapor deposition. Then, the Si substrate 12 was ground to 50 microns as previously mentioned. The Al electrode 86 was subsequently formed by vapor deposition. The thus prepared solar cell using the silicon substrate 12 exhibited very excellent spectral sensitivity as shown in solid line in Fig. 12. Dashed line in the same figure represents a spectral sensitivity curve of a conventional solar cell using a GaAs substrate. The spectral sensitivity of the present Example 8 using the Si substrate 12 is comparable to that of the conventional cell using the GaAs substrate.
Although the gallium arsenide wafers employed for the semiconductor devices of Examples 6-8 use a silicon substrate whose major surface is inclined at 2 to (100), the off angle of the substrates of these examples may be zero. In this case, too, the GaAs layers are given a satisfactory level of crystallinity. Further, the semiconductor devices of Examples 6-8 may use the semiconductor wafers of Examples 2 and 3.
As another modification, the GaAs light emitting layer 54 of Example 6 maty be replaced by a AlGaP layer.
While the present invention has been described in its preferred embodiments with a certain degree of particularity, it is to be understood that the invention is .

~Z92S~V

by no means limited thereto, but various changes, modifications and improvements may be made in the invention, in the light of the foregoing teachings, without departing from the spirit and scope of the invention defined in the appended claims.

~;

` ~, ' ' ' "' :, " "' . :
'

Claims (9)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A semiconductor wafer having an epitaxial GaAs layer, comprising:
a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5° and 5° with respect to (100); and an intermediate layer epitaxially grown on said major surface of said monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between said Si substrate and said epitaxial GaAs layer, the GaAs layer being epitaxially grown on a major surface of a top layer of said intermediate layer, wherein said intermediate layer is selected from (a) a single GaP layer, and (b) a GaP layer formed on said Si substrate; at least one GaP/GaAsP superlattice layer formed on said GaP layer;
and at least one GaAsP/GaAs superlattice layer on said at least one GaP/GaAsP superlattice layer, said epitaxial GaAs layer being formed on said at least one GaAsP/GaAs superlattice layer.
2. A semiconductor wafer according to claim 1 wherein said off angle is between 1° and 3° with respect to (100).
3. A method of producing a semiconductor wafer having an epitaxial GaAs layer comprising the steps of:

preparing a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5° and 5° with respect to (100);
forming a GaP layer by expitaxy on a major surface of said monocrystalline Si substrate;
forming at least one GaP/GaAsP superlattice layer by epitaxy on said GaP layer;
forming at least one GaAsP/GaAs superlattice layer by epitaxy on said at least one GaP/GaAsP superlattice layer;
and forming a GaAs layer by epitaxy on said at least one GaAsP/GaAs superlattice.
4. A method according to claim 3, further comprising annealing said monocrystalline Si substrate by subjecting the Si substrate at a temperature between 600°C and 1100°C, to a flow of PH3 gas for a period ranging from 1 to 60 minutes.
5. A semiconductor light emitting element having an epitaxial GaAs layer, comprising:
a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5° and 5° with respect to (100), an intermediate layer epitaxially grown on a major surface of said monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between said Si substrate and said epitaxial GaAs layer, said epitaxial GaAs layer being epitaxially grown on a major surface of a top layer of said intermediate layer, wherein said intermediate layer is selected from (a) a GaP layer and, (b) a GaP layer formed on said Si substrate; at least one GaP/GaAsP superlattice layer formed on said GaP layer;
and at least one GaAsP/GaAs superlattice layer formed on said at least one GaP/GaAsP superlattice layer, said epitaxial GaAs layer being formed on said at least one GaAsP/GaAs superlattice layer; and a plurality of semiconductor crystalline layers containing GaAs as base elements which are epitaxially grown on said epitaxial GaAs layer and superposed on each other, said crystalline layers including a light emitting layer.
6. A semiconductor light emitting element according to claim 5 having an intermediate layer according to the feature (b), wherein said light emitting layer consists of a semiconductor crystalline layer containing AlGaP as base elements.
7. A semiconductor light emitting element according to claim 5 having an intermediate layer according to the feature (a), wherein said light emitting layer consists of a semiconductor crystalline layer containing GaAs as base elements, and forms a light emitting layer of a semiconductor laser diode.
8. A compound semiconductor device having an epitaxial GaAs layer, comprising:
a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5° and 5° with respect to (100);
an intermediate layer epitaxially grown on said major surface of said monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between said Si substrate and said epitaxial GaAs layer, the GaAs layer being epitaxially grown on a major surface of a top layer of said at least one intermediate layer, wherein said intermediate layer is selected from (a) a GaP layer and (b) a GaP layer formed on said Si substrate; at least one GaP/GaAsP superlattice layer formed on said GaP layer;
and at least one GaAsP/GaAs superlattice layer formed on said at least one GaP/GaAsP superlattice layer, said epitaxial GaAs layer being formed on said at least one GaAsP/GaAs superlattice layer; and at least one semiconductor element formed on said epitaxial GaAs layer.
9. A compound semiconductor device according to claim 8, wherein said at least one semiconductor element comprises at least one of elements selected from the group consisting of: amplifying and/or switching elements including bi-polar transistors and field effect transistors; light emitting elements including light emitting diodes and laser diodes;
light receiving elements including phototransistors; and photovoltaic elements including solar cells.
CA000517386A 1985-09-03 1986-09-03 Epitaxial gallium arsenide semiconductor wafer and method of producing the same Expired - Lifetime CA1292550C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA000616160A CA1322040C (en) 1985-09-03 1991-09-11 Epitaxial gallium arsenide semiconductor wafer and method of producing the same

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP60-195628 1985-09-03
JP19563085A JPS6258616A (en) 1985-09-03 1985-09-03 Arsenide galium epitaxial wafer and manufacture thereof
JP19562885A JPS6258614A (en) 1985-09-03 1985-09-03 Arsenide galium epitaxial wafer and manufacture thereof
JP60-195630 1985-09-03
JP19562985A JPS6258615A (en) 1985-09-03 1985-09-03 Arsenide galium compound semiconductor device
JP60-195629 1985-09-03
JP60-195435 1985-09-04
JP60195435A JPS6258690A (en) 1985-09-04 1985-09-04 Light emitting element of gallium arsenide semiconductor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CA000616160A Division CA1322040C (en) 1985-09-03 1991-09-11 Epitaxial gallium arsenide semiconductor wafer and method of producing the same

Publications (1)

Publication Number Publication Date
CA1292550C true CA1292550C (en) 1991-11-26

Family

ID=27475763

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000517386A Expired - Lifetime CA1292550C (en) 1985-09-03 1986-09-03 Epitaxial gallium arsenide semiconductor wafer and method of producing the same

Country Status (4)

Country Link
US (2) US4928154A (en)
EP (1) EP0214610B1 (en)
CA (1) CA1292550C (en)
DE (1) DE3676019D1 (en)

Families Citing this family (112)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6288318A (en) * 1985-10-14 1987-04-22 Sharp Corp Semiconductor device
JPS63226918A (en) * 1987-03-16 1988-09-21 Shin Etsu Handotai Co Ltd Epitaxial wafer of mixed crystal of gallium arsenide phosphide
US5130269A (en) * 1988-04-27 1992-07-14 Fujitsu Limited Hetero-epitaxially grown compound semiconductor substrate and a method of growing the same
JPH0760791B2 (en) * 1988-11-04 1995-06-28 シャープ株式会社 Compound semiconductor substrate
JPH02235327A (en) * 1989-03-08 1990-09-18 Fujitsu Ltd Device and method of growing semiconductor
JP3114809B2 (en) * 1989-05-31 2000-12-04 富士通株式会社 Semiconductor device
US5164359A (en) * 1990-04-20 1992-11-17 Eaton Corporation Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate
US5281834A (en) * 1990-08-31 1994-01-25 Motorola, Inc. Non-silicon and silicon bonded structure and method of manufacture
US5723871A (en) * 1991-05-02 1998-03-03 Daido Tokushuko Kabushiki Kaisha Process of emitting highly spin-polarized electron beam and semiconductor device therefor
EP0512429B1 (en) * 1991-05-02 1995-01-04 Daido Tokushuko Kabushiki Kaisha Semiconductor device for emitting highly spin-polarized electron beam
US5448084A (en) * 1991-05-24 1995-09-05 Raytheon Company Field effect transistors on spinel substrates
CA2062134C (en) * 1991-05-31 1997-03-25 Ibm Low Defect Densiry/Arbitrary Lattice Constant Heteroepitaxial Layers
US5208182A (en) * 1991-11-12 1993-05-04 Kopin Corporation Dislocation density reduction in gallium arsenide on silicon heterostructures
GB2263814B (en) * 1992-01-17 1996-01-10 Northern Telecom Ltd Semiconductor mixed crystal quantum well device manufacture
FR2691839B1 (en) * 1992-05-27 1994-08-05 Schlumberger Ind Sa HALL EFFECT SENSOR.
US5747862A (en) * 1992-09-25 1998-05-05 Katsumi Kishino Spin-polarized electron emitter having semiconductor opto-electronic layer with split valence band and reflecting mirror
JP2576766B2 (en) * 1993-07-08 1997-01-29 日本電気株式会社 Semiconductor substrate manufacturing method
US5536948A (en) * 1994-08-23 1996-07-16 Grumman Aerospace Corporation Infrared detector element substrate with superlattice layers
US5456206A (en) * 1994-12-07 1995-10-10 Electronics And Telecommunications Research Institute Method for two-dimensional epitaxial growth of III-V compound semiconductors
US5833749A (en) * 1995-01-19 1998-11-10 Nippon Steel Corporation Compound semiconductor substrate and process of producing same
JP3268731B2 (en) * 1996-10-09 2002-03-25 沖電気工業株式会社 Photoelectric conversion element
US5912481A (en) * 1997-09-29 1999-06-15 National Scientific Corp. Heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction
US6423990B1 (en) 1997-09-29 2002-07-23 National Scientific Corporation Vertical heterojunction bipolar transistor
JP3420087B2 (en) * 1997-11-28 2003-06-23 Ｎｅｃエレクトロニクス株式会社 Semiconductor light emitting device
US6563661B2 (en) 2000-02-08 2003-05-13 Seagate Technology Llc Drive-level bearing friction measurement method
US6693033B2 (en) 2000-02-10 2004-02-17 Motorola, Inc. Method of removing an amorphous oxide from a monocrystalline surface
US6392257B1 (en) 2000-02-10 2002-05-21 Motorola Inc. Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
CN1430792A (en) 2000-05-31 2003-07-16 摩托罗拉公司 Semiconductor device and method
US6477285B1 (en) 2000-06-30 2002-11-05 Motorola, Inc. Integrated circuits with optical signal propagation
WO2002003437A1 (en) * 2000-06-30 2002-01-10 Motorola, Inc., A Corporation Of The State Of Delaware Hybrid semiconductor structure and device
US6427066B1 (en) 2000-06-30 2002-07-30 Motorola, Inc. Apparatus and method for effecting communications among a plurality of remote stations
US6410941B1 (en) 2000-06-30 2002-06-25 Motorola, Inc. Reconfigurable systems using hybrid integrated circuits with optical ports
WO2002003436A1 (en) * 2000-06-30 2002-01-10 Motorola, Inc. Thin compound semiconductor structure
US6501973B1 (en) 2000-06-30 2002-12-31 Motorola, Inc. Apparatus and method for measuring selected physical condition of an animate subject
US6555946B1 (en) 2000-07-24 2003-04-29 Motorola, Inc. Acoustic wave device and process for forming the same
AU2001277001A1 (en) 2000-07-24 2002-02-05 Motorola, Inc. Heterojunction tunneling diodes and process for fabricating same
US6638838B1 (en) * 2000-10-02 2003-10-28 Motorola, Inc. Semiconductor structure including a partially annealed layer and method of forming the same
US6583034B2 (en) 2000-11-22 2003-06-24 Motorola, Inc. Semiconductor structure including a compliant substrate having a graded monocrystalline layer and methods for fabricating the structure and semiconductor devices including the structure
US6563118B2 (en) 2000-12-08 2003-05-13 Motorola, Inc. Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same
US20020096683A1 (en) 2001-01-19 2002-07-25 Motorola, Inc. Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate
US6673646B2 (en) 2001-02-28 2004-01-06 Motorola, Inc. Growth of compound semiconductor structures on patterned oxide films and process for fabricating same
US7046719B2 (en) 2001-03-08 2006-05-16 Motorola, Inc. Soft handoff between cellular systems employing different encoding rates
WO2002082551A1 (en) 2001-04-02 2002-10-17 Motorola, Inc. A semiconductor structure exhibiting reduced leakage current
US20020195599A1 (en) * 2001-06-20 2002-12-26 Motorola, Inc. Low-defect semiconductor structure, device including the structure and method for fabricating structure and device
US6709989B2 (en) 2001-06-21 2004-03-23 Motorola, Inc. Method for fabricating a semiconductor structure including a metal oxide interface with silicon
US6992321B2 (en) 2001-07-13 2006-01-31 Motorola, Inc. Structure and method for fabricating semiconductor structures and devices utilizing piezoelectric materials
US6646293B2 (en) 2001-07-18 2003-11-11 Motorola, Inc. Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates
US6693298B2 (en) 2001-07-20 2004-02-17 Motorola, Inc. Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same
US7019332B2 (en) 2001-07-20 2006-03-28 Freescale Semiconductor, Inc. Fabrication of a wavelength locker within a semiconductor structure
US6472694B1 (en) 2001-07-23 2002-10-29 Motorola, Inc. Microprocessor structure having a compound semiconductor layer
US6855992B2 (en) 2001-07-24 2005-02-15 Motorola Inc. Structure and method for fabricating configurable transistor devices utilizing the formation of a compliant substrate for materials used to form the same
US6594414B2 (en) 2001-07-25 2003-07-15 Motorola, Inc. Structure and method of fabrication for an optical switch
US6585424B2 (en) 2001-07-25 2003-07-01 Motorola, Inc. Structure and method for fabricating an electro-rheological lens
US6667196B2 (en) 2001-07-25 2003-12-23 Motorola, Inc. Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method
US6589856B2 (en) 2001-08-06 2003-07-08 Motorola, Inc. Method and apparatus for controlling anti-phase domains in semiconductor structures and devices
US6639249B2 (en) 2001-08-06 2003-10-28 Motorola, Inc. Structure and method for fabrication for a solid-state lighting device
US6462360B1 (en) 2001-08-06 2002-10-08 Motorola, Inc. Integrated gallium arsenide communications systems
US20030034491A1 (en) 2001-08-14 2003-02-20 Motorola, Inc. Structure and method for fabricating semiconductor structures and devices for detecting an object
US6673667B2 (en) 2001-08-15 2004-01-06 Motorola, Inc. Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials
US6730987B2 (en) * 2001-09-10 2004-05-04 Showa Denko K.K. Compound semiconductor device, production method thereof, light-emitting device and transistor
US20030071327A1 (en) 2001-10-17 2003-04-17 Motorola, Inc. Method and apparatus utilizing monocrystalline insulator
WO2003044840A1 (en) * 2001-11-08 2003-05-30 Midwest Research Institute Reactive codoping of gaalinp compound semiconductors
WO2003052836A1 (en) * 2001-12-14 2003-06-26 Midwest Research Institute Multi-junction solar cell device
US7309832B2 (en) * 2001-12-14 2007-12-18 Midwest Research Institute Multi-junction solar cell device
US6916717B2 (en) 2002-05-03 2005-07-12 Motorola, Inc. Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate
US20060162768A1 (en) * 2002-05-21 2006-07-27 Wanlass Mark W Low bandgap, monolithic, multi-bandgap, optoelectronic devices
US8173891B2 (en) * 2002-05-21 2012-05-08 Alliance For Sustainable Energy, Llc Monolithic, multi-bandgap, tandem, ultra-thin, strain-counterbalanced, photovoltaic energy converters with optimal subcell bandgaps
US8067687B2 (en) * 2002-05-21 2011-11-29 Alliance For Sustainable Energy, Llc High-efficiency, monolithic, multi-bandgap, tandem photovoltaic energy converters
US7169619B2 (en) 2002-11-19 2007-01-30 Freescale Semiconductor, Inc. Method for fabricating semiconductor structures on vicinal substrates using a low temperature, low pressure, alkaline earth metal-rich process
US6885065B2 (en) 2002-11-20 2005-04-26 Freescale Semiconductor, Inc. Ferromagnetic semiconductor structure and method for forming the same
WO2004049459A1 (en) * 2002-11-25 2004-06-10 The University Of Toledo Integrated photoelectrochemical cell and system having a solid polymer electrolyte
JP2006508253A (en) * 2002-11-27 2006-03-09 ザ・ユニバーシティ・オブ・トレド Integrated photoelectrochemistry with liquid electrolyte and its system
US7020374B2 (en) 2003-02-03 2006-03-28 Freescale Semiconductor, Inc. Optical waveguide structure and method for fabricating the same
US6965128B2 (en) 2003-02-03 2005-11-15 Freescale Semiconductor, Inc. Structure and method for fabricating semiconductor microresonator devices
US6786390B2 (en) * 2003-02-04 2004-09-07 United Epitaxy Company Ltd. LED stack manufacturing method and its structure thereof
JP2004265945A (en) * 2003-02-21 2004-09-24 Sumitomo Chem Co Ltd Quality determination method of semiconductor epitaxial crystal wafer and wafer manufacturing method using the same
US7109465B2 (en) * 2003-04-04 2006-09-19 Avago Technologies Ecbu Ip (Singapore) Pte., Ltd. System and method for converting ambient light energy into a digitized electrical output signal for controlling display and keypad illumination on a battery powered system
US7667133B2 (en) * 2003-10-29 2010-02-23 The University Of Toledo Hybrid window layer for photovoltaic cells
US20080223439A1 (en) * 2004-02-19 2008-09-18 Xunming Deng Interconnected Photoelectrochemical Cell
US20060011129A1 (en) * 2004-07-14 2006-01-19 Atomic Energy Council - Institute Of Nuclear Energy Research Method for fabricating a compound semiconductor epitaxial wafer
US8772628B2 (en) 2004-12-30 2014-07-08 Alliance For Sustainable Energy, Llc High performance, high bandgap, lattice-mismatched, GaInP solar cells
WO2006110613A2 (en) * 2005-04-11 2006-10-19 The University Of Toledo Integrated photovoltaic-electrolysis cell
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
KR100641063B1 (en) * 2005-08-26 2006-11-01 삼성전자주식회사 Method of manufacturing a single crystalline structure and method of manufacturing a semiconductor device by using the same
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US20070252216A1 (en) * 2006-04-28 2007-11-01 Infineon Technologies Ag Semiconductor device and a method of manufacturing such a semiconductor device
EP2062290B1 (en) 2006-09-07 2019-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Defect reduction using aspect ratio trapping
US7541105B2 (en) * 2006-09-25 2009-06-02 Seagate Technology Llc Epitaxial ferroelectric and magnetic recording structures including graded lattice matching layers
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US20080187018A1 (en) 2006-10-19 2008-08-07 Amberwave Systems Corporation Distributed feedback lasers formed via aspect ratio trapping
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US9508890B2 (en) * 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
JP2010538495A (en) 2007-09-07 2010-12-09 アンバーウェーブ・システムズ・コーポレーション Multi-junction solar cell
US8344354B2 (en) * 2008-03-25 2013-01-01 National University Corporation Nagoya University Spin-polarized electron source
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
WO2010033813A2 (en) 2008-09-19 2010-03-25 Amberwave System Corporation Formation of devices by epitaxial layer overgrowth
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
US8912428B2 (en) * 2008-10-22 2014-12-16 Epir Technologies, Inc. High efficiency multijunction II-VI photovoltaic solar cells
EP2415083B1 (en) 2009-04-02 2017-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Devices formed from a non-polar plane of a crystalline material and method of making the same
US20110073887A1 (en) * 2009-09-25 2011-03-31 Alliance For Sustainable Energy, Llc Optoelectronic devices having a direct-band-gap base and an indirect-band-gap emitter
TWI565063B (en) 2010-10-01 2017-01-01 應用材料股份有限公司 Gallium arsenide based materials used in thin film transistor applications
WO2012051324A1 (en) 2010-10-12 2012-04-19 Alliance For Sustainable Energy, Llc High bandgap iii-v alloys for high efficiency optoelectronics
DE102011107657A1 (en) 2011-07-12 2013-01-17 Nasp Iii/V Gmbh Monolithic integrated semiconductor structure
US9590131B2 (en) 2013-03-27 2017-03-07 Alliance For Sustainable Energy, Llc Systems and methods for advanced ultra-high-performance InP solar cells
EP3036770B1 (en) * 2013-08-23 2022-03-02 Intel Corporation High resistance layer for iii-v channel deposited on group iv substrates for mos transistors

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2225207B1 (en) * 1973-04-16 1978-04-21 Ibm
US4120706A (en) * 1977-09-16 1978-10-17 Harris Corporation Heteroepitaxial deposition of gap on silicon substrates
US4675709A (en) * 1982-06-21 1987-06-23 Xerox Corporation Quantized layered structures with adjusted indirect bandgap transitions
JPS5973499A (en) * 1982-10-15 1984-04-25 Agency Of Ind Science & Technol Growth of compound semiconductor
JPS6012724A (en) * 1983-07-01 1985-01-23 Agency Of Ind Science & Technol Growing method of compound semiconductor
US4632712A (en) * 1983-09-12 1986-12-30 Massachusetts Institute Of Technology Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth
US4558336A (en) * 1984-03-02 1985-12-10 The United States Of America As Represented By The Secretary Of The Army MBE Growth technique for matching superlattices grown on GaAs substrates
JPS6191098A (en) * 1984-10-09 1986-05-09 Daido Steel Co Ltd Gallium arsenide crystal grown on silicon base and method thereof
JPS61145820A (en) * 1984-12-20 1986-07-03 Seiko Epson Corp Semiconductor thin film material
JPS621224A (en) * 1985-06-26 1987-01-07 Sharp Corp Semiconductor element structure
US4774205A (en) * 1986-06-13 1988-09-27 Massachusetts Institute Of Technology Monolithic integration of silicon and gallium arsenide devices
US4835116A (en) * 1987-11-13 1989-05-30 Kopin Corporation Annealing method for III-V deposition
US4826784A (en) * 1987-11-13 1989-05-02 Kopin Corporation Selective OMCVD growth of compound semiconductor materials on silicon substrates

Also Published As

Publication number Publication date
US4963508A (en) 1990-10-16
EP0214610B1 (en) 1990-12-05
US4928154A (en) 1990-05-22
DE3676019D1 (en) 1991-01-17
EP0214610A2 (en) 1987-03-18
EP0214610A3 (en) 1987-12-02

Similar Documents

Publication Publication Date Title
CA1292550C (en) Epitaxial gallium arsenide semiconductor wafer and method of producing the same
US7071015B2 (en) Semiconductor light emitting device and method for producing the same
US9449868B2 (en) Methods of forming semiconductor diodes by aspect ratio trapping with coalesced films
US5221413A (en) Method for making low defect density semiconductor heterostructure and devices made thereby
US7084421B2 (en) Light-emitting device using group III nitride group compound semiconductor
US5442205A (en) Semiconductor heterostructure devices with strained semiconductor layers
EP0383215A2 (en) Epitaxial-growth structure for a semiconductor light-emitting device, and semiconductor light-emitting device using the same
JPH10321911A (en) Method for manufacturing epitaxial layer of compound semiconductor on single-crystal silicon and light-emitting diode manufactured therewith
CA1199097A (en) Preparation of photodiodes
US3985590A (en) Process for forming heteroepitaxial structure
US5107317A (en) Semiconductor device with first and second buffer layers
US5308444A (en) Method of making semiconductor heterostructures of gallium arsenide on germanium
JP3207918B2 (en) Light-emitting device using polycrystalline semiconductor material of group III-V compound and method for manufacturing the same
US5445897A (en) Epitaxial wafer and process for producing the same
KR100433039B1 (en) Epitaxial wafer and manufacturing method thereof
US3984857A (en) Heteroepitaxial displays
CA1322040C (en) Epitaxial gallium arsenide semiconductor wafer and method of producing the same
US6218681B1 (en) Gallium arsenide phosphide epitaxial wafer and light emitting diode
JPH0434920A (en) Hetero epitaxial growth method for group iii-v compound semiconductor on different type board
CN114242851A (en) Semiconductor device and manufacturing method thereof
JP3625677B2 (en) Epitaxial wafer, light emitting diode, and manufacturing method thereof
JP2001036133A (en) Epitaxial wafer and light-emitting diode
JPS6258615A (en) Arsenide galium compound semiconductor device
JPH05218496A (en) Semiconductor light emitting element
JPH01225313A (en) Semiconductor material

Legal Events

Date Code Title Description
MKLA Lapsed
MKLA Lapsed

Effective date: 19971126