CA1282152C - Digital circuit- and packet-switching network and switching facility therefor - Google Patents
Digital circuit- and packet-switching network and switching facility thereforInfo
- Publication number
- CA1282152C CA1282152C CA000557553A CA557553A CA1282152C CA 1282152 C CA1282152 C CA 1282152C CA 000557553 A CA000557553 A CA 000557553A CA 557553 A CA557553 A CA 557553A CA 1282152 C CA1282152 C CA 1282152C
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- CA
- Canada
- Prior art keywords
- switching
- packet
- input
- facility
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/64—Hybrid switching systems
Abstract
ABSTRACT
A digital switching network is disclosed in which paths can be preset from any inlet to any outlet either for circuit-switched connections or for packet-switched messages (packets), as required. At any point in time, the paths preset for the packet.-switched messages form a network whose nodes lie in the switching facilities of the switching network. The switching facilities contain the functional units required to switch each data packet on the path preset for it. This makes it possible to dynamically divide a single switching network into a circuit-switching network and a packet-switching network as required.
A digital switching network is disclosed in which paths can be preset from any inlet to any outlet either for circuit-switched connections or for packet-switched messages (packets), as required. At any point in time, the paths preset for the packet.-switched messages form a network whose nodes lie in the switching facilities of the switching network. The switching facilities contain the functional units required to switch each data packet on the path preset for it. This makes it possible to dynamically divide a single switching network into a circuit-switching network and a packet-switching network as required.
Description
The present invention relates to a digital switchiny network and to a switching facility therefor.
To an increasing extent, digital equipment is being used for the transmission of information. Moreover, data transmlsslon is gaining increasing slgnlficance. To meet anticipated future requirements, therefore, a communicatlon network is needed which is equally well suited to switching different type~ of information. The services to be integrated in such a network differ in various ways. For example, one can distinguish between services where a fairly steady informatlon flow exists during rela~ively short periods of time, and serviceæ where information flows brlefly from time to time over prolonged periods of time.
There are two differen~ switching methods adapted to those requirements. A switching me~hod in which a direct transmission path between the terminals involved is made available for the duration of a call, regardless of whether information is transmitted or not, is called "circuit switching". A switching method in which the messages are div~ded into packets and routed through the network link by linX with ~he aid of destination information contained in a packet header is called "packet ~witching". The packets are stored until a path ln a desixed direction becomes free. There is no through-switching of transmission paths. A special case is store-and-forward switching, where undivided messages are routed through the data network link by link from switching center to swltching center, e.g. r in electronic mail systems. More formal definitions are .. ~
. ,: .: .
5~
contained in "NT~-Empfehlung 0902", 1982, items 4.2.1 and 4.2.2 (published in "ntz," No. 8/82, page 549).
Obviously the switchlng equipment must be comparable with the particular switching method utilized.
One way o~ performing both circuit--s~itchirlcJ arld packet switching is described in an article by A. C'halet and R. Drignath, "Datenmodul-Architek~ur mit Paketverarbeitungs~unktionen,"
Elektrisches Nachrichtenwesen, Vol. 59, No. 1/2, 1985. In that system, packet-switching is effected by storing each packet in a packet memory at the input of ~he switching center, then setting up a path through the switching network like in a circuit-switching syste~, then transmitting the packet over this path, and finally clearing this path. To accelerate the setting up of a path for each packet, the parameters necessary for call setup (in particular, the destination address) are determlned in a call setup phase and are s~ored so as to be immediately available upon arrival of a packet.
A completely different proposal was presented by John J.
Kulzer and warren A. Montgomery at the ISS '8~ Florence, 7-11 May 198~, in a paper entitled "Statistical Switching Architectures for Future Services" (Session ~3 A Paper 1). A similar proposal was submitted at the same conference by A. Thomas et al., "Asynchronous Time-Division Techniques. an Experimental Packet Network Integrating Videocommunica~ion" (Session 32 C Paper 2).
According to those proposals, all information, from sporadically occurring single instructlons to digitized video signals, is divided into packets and passed on by packet-switching. ~ccording .5~
7~30-70 to Figure 6 of the Kulzer article and the pertinent description, the individual packets are routed through an exchange from stage to stage, where they are temporarily stored as required.
Both prior art solutlons outlined ahove have advankages and disadvan~ages. If signals have ~o be switched at hiyh transmission speeds (so-called broadband swlkchlny), some o~ -tho~e advantages and disadvantages are particularly significant.
It will thus be appreciated that overall objectives o~
the present invention are to provide a novel switching network and a related novel switching facility which combine many advantages of both circuit-switching and packet-switching to provide significan~ lmprovemen~s over the prior art.
A digital switching network constructed in accordance with the invention is so designed that paths from any inlet to any outlet can either be set up for circuit-switched connections or be preset for packet-switched messages (packets), as required. At any given point of time, the paths preset for packet-switched messages ~orm a network whose nodes lie in the switching facilities of the switching ne~work. The switching facilities contain the functional units required to switch each packet on its particular preset path.
This makes it possible to dyna~ically divide a single switching network into a circuit-switching network and a packet-switching network as required.
Not only the structure of such a swi~ching network, but also its construction with circuit hoards, connectors, racksl and wiring are essentially ~he same as in a pure circuit-swi~chlng 72~30-70 network or a pure packet-swi~ching ne~work. Compared -to a pure circuit-switching network or a pure packet-swi~chiny network, additional circuitry i~ reguired only in those modules which contain the crosspQlnts. In modern switching equipment, the switch facility modules are typlcally implemented as larye-scale in~egrated circuits. The additional circui~ry reyuired to practice the present inventlon results in a slight increase in the circuit complexity of such modules, but without any change in the number and arrangement of terminal pillS; although the control of such a switching facility, which is under program control, and/or possibly enhanced power supply may add slightly to the expense of the required equipment. With such a relatively sligh~ additional expenditure, however, both packet-switched and circuit-switched connections can be established as required.
The invention may be summarized, according to one aspect, as in a digital switching network having a plurality of inlets and outlets and a plurality of switching factlities each having a plurality of inputs and outputs through which possible paths for circuit-switched connection can be set up, each such possible path extending from a respective network inlet through at least one respectlve switching facllity via an associated input and an associated output to a respective network outlet, with two of said possible paths for circuit-switched connections converging or diverging at a common said switching facility in which said two possible paths converge from a first pair of inputs of said common switching facility into a first single output of said common switching facility or in which said two posslhle paths diverge ~L~8~,~5;~
from a single input of said common switchiny facility in~o a pair of outputs of said common switching facility, the improvement comprising: packet--switching setup means ~or designatiny on demand both of said two possible paths for circuit-switched connec-tions as two respec~ive preset packet--switched paths that are temporarily simultaneously available on demand for pa~ket-swikahecl messages each comprisiny one or more data packets identified with one or the other of said respective preset paths, and packet-switching means associated with at least said common switching facility for switching data packets identified with each of said two preset paths from the respective switching facillty input associated with said each path to the respective switching facility output associated with said each path.
According to another aspect, the invention provides a combined circuit-switching and packet-switching facility comprising a plurality of input channels, a plurality of output channels, a switching matrix comprising a first se~ of crosspoint elements for connecting each output channel with every input channel, switching control logic responsive to external circuit-switched control signals for controlling the first set ofcrosspoint elements to thereby effect one or more relatively permanent circui~--swltched connections between designated ones of said input channels and respective designa~ed ones of said output channels, and a packet-handling unit comprising input selection means for connecting an input of the packet-handling uni~ to a selected one of the input channels, address decoder means for determining an associated one of said output channels from the ~.}i,~
~x~s~
72~30 70 information contained in a header of an input packet appearing at ~he selected input channel, and packet logic control means responsive to the address decoder means for causlng the switchiny control logic ~o establish, for no longer than the duration of a single packe-t, a temporary packet-swltched connection from ~he selected input channel to the output channel a~.so~iated wlth ~aid input packet.
The Figure shows a block diagram of an exemplary broadband switching module constructed in accordance with the invention.
The invention will be described in the context of a space-division multiplex broadband switching network in which the s~itching facilities are designed as broadband integrated swi~ching modules; ~irst the switching module ~switching facility) and then the switc~ing network will be described.
However, it will be understood that the teachings of the invention are not necessarily limited either to broadband applications (more correctly: high-data-rate applications) or to space-division ~ultiplex switching. The terms used herein, such as input, outpu~, channel, path, and connection, should ~hus be understood as broadly referring to terminals, pins, conductvr tracks, and time slots (in a TDM signal).
Reference should now be made to the Figure, which shows a block diagram of a broadband switching module 40 as an example of a switching facility in accordance with the invention.
The broadband switching 5a ~ 8~
module 40 has 16 s;gnals ;nputs E1 ~.. E16 and a clock ;nput TE. These inputs are followed by an input isolation amplifier 3. For the signals coming frorn the s;gnal inputs E1 ... E16, the ;nput isolation amplifier 3 is followed by an input synchronizer 1. Also applied to the inp~t synchronizer 1 is the clock T from the cLock input TE, which was conditioned in the input isolation ampLifier 3. Thus, bit-synchronous digital signals appear at the outputs of the input synchronizer 1. These outputs are connected to the column lines of a switching matrix K. The row lines of this sw;tching matr;x K are connected to inputs of an output synchron;zer 2, in which the s;gnals are (bit-)syn-chron;zed with the clock T again. These signals and the clock T pass through an output isolation amplifier 4 to signal outputs A1 ... A16 and a clock output TA.
CrGsspoints at the intersections of column lines and row lines in the switching matrix K are controlled by a decode and control logic 6 tdouble lines in the f;gure). The broadband switching module 40 is con-trolled and monitored v;a a control bus BUS by means of the decode and control logic 6.
This broadband switching module 40, which contalns all devices necessary for circuit switch;ng, is supplemented with devices which alternatively permit packet sw;tch-;ng. The most important unit for this purpose is a packet-handling unit P. The embodiment assumes that a maximum of three quarters of the signal paths is needed for packet sw;tching. The packet-handling unit P therefore contains four subunits P1 ..~ P4, each of which has a s1gnal input that can be connected by means D sottle-H.Preisach-K~chrodi 11-2-2 82~
of a first packet-switching matrix PK1 to a column l;ne coming from any of the signal inputs E1 .~ E16.
If the number of subunits is equal to the number of signal inputs, the first packet-switching matrix PK1 is replaced by direct connections~
As packet-switching devices are known per se, the tasks and the basic design of the packet-handl;ng un;t P and the subunits contained therein, P1 n~ P4~ are known ;n pr;nciple, too. The main task of the handling unit P is to determine the further path for each packet and to route this paGket over this path, i.e., to a par-ticular signal output A1 .~. A16. First of all it is necessary to identify the packets as such, ~hich ne-cess;tates detecting the start of a new packet. For this synchronization task, a wide variety of solutions is ava;lable. In principle, each packet consists of two parts.The first part, which is usually also the first In time and precedes the packet as a header, con-tains all data required to control the exchange of in-format;on. The second part cbntains the information it-self. The first part (header) must at least contain the data required to determine the further path~ In addition,` ;t may serve for synchronization or con-ta;n data on the sender, for example. Whether the header of the packet remains unchanged all the way from the sender to the recipient and then contalns all data necessary for this purpose or whether the header is renewed link by link by preset information is irrelevant to the present inVention. If a packet has a predetermined length" for example, all packets in the D.~ott~e-HOPreisach-K.Schrodi 11-2-2 ~8~
switching network may be in synchronism, which would make it possible to apply to all broadband switching modules of the switching net~ork an external signal marking the start of a packet. If, at the input of the switching network, the packet is then provided w;th a header containing two bits for each stage of the switching network and, thus, for each broadband switching module 40to be traversed by the packet, which each serve to select one of the ~our possible signal outputs, the handling unit P can be of very simple design. The handling unit P is then in a position to determine the instant at which the two address bits intended for th;s broadband switching module appear. These and the pre-ceding address bits, which were needed to address the preceding stages, need not be passed on to the following stages~ It is therefore suffiGient to trans-fer the packet to the proper signal output onLy ;f these two address bits were evaluated. In that case, the through-connection may take place in the switching matrix K~ The handling unit P must then sPlect one of the 16 signal outputs A1 .~. A16 from the ~wo received address bits in an address decoder PA and cause the decode and control logic 6 to activate the appropriate crosspoint of the switching matrix K~
In practice, however, a handling unit P of such simple des;qn meetsonly quite simple requirements. Losses occur in it already if two packets simultaneously arriving at two different sigoal inputs E1 ... E16 have to be routed to the same signal output. In that case, the packet which cannot be switched through immediately should be D.~ottle-H.Preisach-K.Schrodi 11-2-2 ~8~5~
_ 9 _ temporarily stored and then passed on. Th;s requires su;table buffers ;n the subunits P1 ~.~ P4. Further-more, output must be possible from the subunits P1 ... P4 to the signal outputs A1 ... A16. For this pur pose, a second packet-switching matr;x PKZ is provided.
The crosspoints of this second packet-switching matrix PK2 are controlled from the decode and control logic 6.
The size of the buffers in the subunits P1 ... P4 de-pends on the traffic volume expected and the grade of service required. The greater the traffic volume to be expected and the higher the required grade of service, the larger the buffers w;ll have to be. In principle, however, the rapac;ties of the buffers cannot be such that it is certain that no incoming packet will be lost.
In case of need, therefore, it must be ensured~ e.g., in the terminals, that the lost packets will be sup-plied subsequently. It is also possible for the decode and control logic 6 to repor~ an imminent or already existing overload via the control bus B~S to the out-side in order to request further paths for switching packets. For this, use can also be made, at least for some links, of paths set up by circuit switching.
However, buffers are also necessary, for example, if the start of a packet must first be determined from the contents of the incoming data stream and if, never-theless, the entire packet must be switched throughO
If packet switching is to be performed as described in the above-mentioned article by A~ Thomas et al with the aid of Fig. 9 of that artic~e, the subunits P1 .~. P4 must also contain the functional units for synchronization.
D.90ttle-H.Preisach-K.Schrodi 11 2-2 8~
In that case, in wh;ch the packets are so delayed that a broadband switching module 40 has to pro-cess the header of only a s;ngle packet at a time, the amount of c;rcuitry required in the handl;ng unit P and the decode and control logic 6 can be kept relatively small. It is suffic;ent, for example, if the address decoder PA is addressable from only one of the subunits P1 a~ P4 at a time~ Also, in the sec-ond packet-sw;tch;ng matrix PKZ, the decode and con-trol logic 6 never has to activate two crosspoints at a t;me. Even if the header of a packet contains address information for only one link and the address must be changed ;n the handling unit P, the amount of circuitry required in the necessary modules will be smaller if it is never necessary to process two headers at a time.
~n the embodiment, which shows a broadband switching module, i.e., a module operating at high speed, the combination of circuit switching and packet switching in accordance with the invention, unlike true circuit switching, requires that the crosspoints can be activat-ed quickly. At least part of the decode and control logic 6 must, therefore, be capable of operating at a speed apprGximately equal to the transmission speed.
For this reason, the decode and control logic 6 is di-v;ded into a slow portion 61 and a fast portior, 62~
The crosspoints in the first packet-switching matrix PK1 and in the switching matrix K are activated ~rom the slow portion 61, and those in the second packet-switching matrix PK2 from the fast por~ion 6Z~ The D.Bottle-H.Preisach-K.Schrodi 11-2 Z
8,V~
packet-handling unit P cooperates primarily with the fast portion 6Z.
In a digital switching network according to the inven-tion, the broadband switching modules described can be used as switching facilities. By some kind of central or decentralized control, paths for circuit-switched connections can be freely set up in a conventional manner. Alternatively, such paths can be preset for packet-switched messages. To this end, in each broad-band sw;tching module through which such a path is to lead, the ~irst packet-switching matrix PK1 must connect one of the subunits P1 ... P4 of the handling unit P to this path. In addition, the address decoder PA must be fed with the data required to properly route the packets subsequently to be switched on the path to be preset.
D~Battle-H.Preisach-K~Schrodi 11-Z-2 , .
To an increasing extent, digital equipment is being used for the transmission of information. Moreover, data transmlsslon is gaining increasing slgnlficance. To meet anticipated future requirements, therefore, a communicatlon network is needed which is equally well suited to switching different type~ of information. The services to be integrated in such a network differ in various ways. For example, one can distinguish between services where a fairly steady informatlon flow exists during rela~ively short periods of time, and serviceæ where information flows brlefly from time to time over prolonged periods of time.
There are two differen~ switching methods adapted to those requirements. A switching me~hod in which a direct transmission path between the terminals involved is made available for the duration of a call, regardless of whether information is transmitted or not, is called "circuit switching". A switching method in which the messages are div~ded into packets and routed through the network link by linX with ~he aid of destination information contained in a packet header is called "packet ~witching". The packets are stored until a path ln a desixed direction becomes free. There is no through-switching of transmission paths. A special case is store-and-forward switching, where undivided messages are routed through the data network link by link from switching center to swltching center, e.g. r in electronic mail systems. More formal definitions are .. ~
. ,: .: .
5~
contained in "NT~-Empfehlung 0902", 1982, items 4.2.1 and 4.2.2 (published in "ntz," No. 8/82, page 549).
Obviously the switchlng equipment must be comparable with the particular switching method utilized.
One way o~ performing both circuit--s~itchirlcJ arld packet switching is described in an article by A. C'halet and R. Drignath, "Datenmodul-Architek~ur mit Paketverarbeitungs~unktionen,"
Elektrisches Nachrichtenwesen, Vol. 59, No. 1/2, 1985. In that system, packet-switching is effected by storing each packet in a packet memory at the input of ~he switching center, then setting up a path through the switching network like in a circuit-switching syste~, then transmitting the packet over this path, and finally clearing this path. To accelerate the setting up of a path for each packet, the parameters necessary for call setup (in particular, the destination address) are determlned in a call setup phase and are s~ored so as to be immediately available upon arrival of a packet.
A completely different proposal was presented by John J.
Kulzer and warren A. Montgomery at the ISS '8~ Florence, 7-11 May 198~, in a paper entitled "Statistical Switching Architectures for Future Services" (Session ~3 A Paper 1). A similar proposal was submitted at the same conference by A. Thomas et al., "Asynchronous Time-Division Techniques. an Experimental Packet Network Integrating Videocommunica~ion" (Session 32 C Paper 2).
According to those proposals, all information, from sporadically occurring single instructlons to digitized video signals, is divided into packets and passed on by packet-switching. ~ccording .5~
7~30-70 to Figure 6 of the Kulzer article and the pertinent description, the individual packets are routed through an exchange from stage to stage, where they are temporarily stored as required.
Both prior art solutlons outlined ahove have advankages and disadvan~ages. If signals have ~o be switched at hiyh transmission speeds (so-called broadband swlkchlny), some o~ -tho~e advantages and disadvantages are particularly significant.
It will thus be appreciated that overall objectives o~
the present invention are to provide a novel switching network and a related novel switching facility which combine many advantages of both circuit-switching and packet-switching to provide significan~ lmprovemen~s over the prior art.
A digital switching network constructed in accordance with the invention is so designed that paths from any inlet to any outlet can either be set up for circuit-switched connections or be preset for packet-switched messages (packets), as required. At any given point of time, the paths preset for packet-switched messages ~orm a network whose nodes lie in the switching facilities of the switching ne~work. The switching facilities contain the functional units required to switch each packet on its particular preset path.
This makes it possible to dyna~ically divide a single switching network into a circuit-switching network and a packet-switching network as required.
Not only the structure of such a swi~ching network, but also its construction with circuit hoards, connectors, racksl and wiring are essentially ~he same as in a pure circuit-swi~chlng 72~30-70 network or a pure packet-swi~ching ne~work. Compared -to a pure circuit-switching network or a pure packet-swi~chiny network, additional circuitry i~ reguired only in those modules which contain the crosspQlnts. In modern switching equipment, the switch facility modules are typlcally implemented as larye-scale in~egrated circuits. The additional circui~ry reyuired to practice the present inventlon results in a slight increase in the circuit complexity of such modules, but without any change in the number and arrangement of terminal pillS; although the control of such a switching facility, which is under program control, and/or possibly enhanced power supply may add slightly to the expense of the required equipment. With such a relatively sligh~ additional expenditure, however, both packet-switched and circuit-switched connections can be established as required.
The invention may be summarized, according to one aspect, as in a digital switching network having a plurality of inlets and outlets and a plurality of switching factlities each having a plurality of inputs and outputs through which possible paths for circuit-switched connection can be set up, each such possible path extending from a respective network inlet through at least one respectlve switching facllity via an associated input and an associated output to a respective network outlet, with two of said possible paths for circuit-switched connections converging or diverging at a common said switching facility in which said two possible paths converge from a first pair of inputs of said common switching facility into a first single output of said common switching facility or in which said two posslhle paths diverge ~L~8~,~5;~
from a single input of said common switchiny facility in~o a pair of outputs of said common switching facility, the improvement comprising: packet--switching setup means ~or designatiny on demand both of said two possible paths for circuit-switched connec-tions as two respec~ive preset packet--switched paths that are temporarily simultaneously available on demand for pa~ket-swikahecl messages each comprisiny one or more data packets identified with one or the other of said respective preset paths, and packet-switching means associated with at least said common switching facility for switching data packets identified with each of said two preset paths from the respective switching facillty input associated with said each path to the respective switching facility output associated with said each path.
According to another aspect, the invention provides a combined circuit-switching and packet-switching facility comprising a plurality of input channels, a plurality of output channels, a switching matrix comprising a first se~ of crosspoint elements for connecting each output channel with every input channel, switching control logic responsive to external circuit-switched control signals for controlling the first set ofcrosspoint elements to thereby effect one or more relatively permanent circui~--swltched connections between designated ones of said input channels and respective designa~ed ones of said output channels, and a packet-handling unit comprising input selection means for connecting an input of the packet-handling uni~ to a selected one of the input channels, address decoder means for determining an associated one of said output channels from the ~.}i,~
~x~s~
72~30 70 information contained in a header of an input packet appearing at ~he selected input channel, and packet logic control means responsive to the address decoder means for causlng the switchiny control logic ~o establish, for no longer than the duration of a single packe-t, a temporary packet-swltched connection from ~he selected input channel to the output channel a~.so~iated wlth ~aid input packet.
The Figure shows a block diagram of an exemplary broadband switching module constructed in accordance with the invention.
The invention will be described in the context of a space-division multiplex broadband switching network in which the s~itching facilities are designed as broadband integrated swi~ching modules; ~irst the switching module ~switching facility) and then the switc~ing network will be described.
However, it will be understood that the teachings of the invention are not necessarily limited either to broadband applications (more correctly: high-data-rate applications) or to space-division ~ultiplex switching. The terms used herein, such as input, outpu~, channel, path, and connection, should ~hus be understood as broadly referring to terminals, pins, conductvr tracks, and time slots (in a TDM signal).
Reference should now be made to the Figure, which shows a block diagram of a broadband switching module 40 as an example of a switching facility in accordance with the invention.
The broadband switching 5a ~ 8~
module 40 has 16 s;gnals ;nputs E1 ~.. E16 and a clock ;nput TE. These inputs are followed by an input isolation amplifier 3. For the signals coming frorn the s;gnal inputs E1 ... E16, the ;nput isolation amplifier 3 is followed by an input synchronizer 1. Also applied to the inp~t synchronizer 1 is the clock T from the cLock input TE, which was conditioned in the input isolation ampLifier 3. Thus, bit-synchronous digital signals appear at the outputs of the input synchronizer 1. These outputs are connected to the column lines of a switching matrix K. The row lines of this sw;tching matr;x K are connected to inputs of an output synchron;zer 2, in which the s;gnals are (bit-)syn-chron;zed with the clock T again. These signals and the clock T pass through an output isolation amplifier 4 to signal outputs A1 ... A16 and a clock output TA.
CrGsspoints at the intersections of column lines and row lines in the switching matrix K are controlled by a decode and control logic 6 tdouble lines in the f;gure). The broadband switching module 40 is con-trolled and monitored v;a a control bus BUS by means of the decode and control logic 6.
This broadband switching module 40, which contalns all devices necessary for circuit switch;ng, is supplemented with devices which alternatively permit packet sw;tch-;ng. The most important unit for this purpose is a packet-handling unit P. The embodiment assumes that a maximum of three quarters of the signal paths is needed for packet sw;tching. The packet-handling unit P therefore contains four subunits P1 ..~ P4, each of which has a s1gnal input that can be connected by means D sottle-H.Preisach-K~chrodi 11-2-2 82~
of a first packet-switching matrix PK1 to a column l;ne coming from any of the signal inputs E1 .~ E16.
If the number of subunits is equal to the number of signal inputs, the first packet-switching matrix PK1 is replaced by direct connections~
As packet-switching devices are known per se, the tasks and the basic design of the packet-handl;ng un;t P and the subunits contained therein, P1 n~ P4~ are known ;n pr;nciple, too. The main task of the handling unit P is to determine the further path for each packet and to route this paGket over this path, i.e., to a par-ticular signal output A1 .~. A16. First of all it is necessary to identify the packets as such, ~hich ne-cess;tates detecting the start of a new packet. For this synchronization task, a wide variety of solutions is ava;lable. In principle, each packet consists of two parts.The first part, which is usually also the first In time and precedes the packet as a header, con-tains all data required to control the exchange of in-format;on. The second part cbntains the information it-self. The first part (header) must at least contain the data required to determine the further path~ In addition,` ;t may serve for synchronization or con-ta;n data on the sender, for example. Whether the header of the packet remains unchanged all the way from the sender to the recipient and then contalns all data necessary for this purpose or whether the header is renewed link by link by preset information is irrelevant to the present inVention. If a packet has a predetermined length" for example, all packets in the D.~ott~e-HOPreisach-K.Schrodi 11-2-2 ~8~
switching network may be in synchronism, which would make it possible to apply to all broadband switching modules of the switching net~ork an external signal marking the start of a packet. If, at the input of the switching network, the packet is then provided w;th a header containing two bits for each stage of the switching network and, thus, for each broadband switching module 40to be traversed by the packet, which each serve to select one of the ~our possible signal outputs, the handling unit P can be of very simple design. The handling unit P is then in a position to determine the instant at which the two address bits intended for th;s broadband switching module appear. These and the pre-ceding address bits, which were needed to address the preceding stages, need not be passed on to the following stages~ It is therefore suffiGient to trans-fer the packet to the proper signal output onLy ;f these two address bits were evaluated. In that case, the through-connection may take place in the switching matrix K~ The handling unit P must then sPlect one of the 16 signal outputs A1 .~. A16 from the ~wo received address bits in an address decoder PA and cause the decode and control logic 6 to activate the appropriate crosspoint of the switching matrix K~
In practice, however, a handling unit P of such simple des;qn meetsonly quite simple requirements. Losses occur in it already if two packets simultaneously arriving at two different sigoal inputs E1 ... E16 have to be routed to the same signal output. In that case, the packet which cannot be switched through immediately should be D.~ottle-H.Preisach-K.Schrodi 11-2-2 ~8~5~
_ 9 _ temporarily stored and then passed on. Th;s requires su;table buffers ;n the subunits P1 ~.~ P4. Further-more, output must be possible from the subunits P1 ... P4 to the signal outputs A1 ... A16. For this pur pose, a second packet-switching matr;x PKZ is provided.
The crosspoints of this second packet-switching matrix PK2 are controlled from the decode and control logic 6.
The size of the buffers in the subunits P1 ... P4 de-pends on the traffic volume expected and the grade of service required. The greater the traffic volume to be expected and the higher the required grade of service, the larger the buffers w;ll have to be. In principle, however, the rapac;ties of the buffers cannot be such that it is certain that no incoming packet will be lost.
In case of need, therefore, it must be ensured~ e.g., in the terminals, that the lost packets will be sup-plied subsequently. It is also possible for the decode and control logic 6 to repor~ an imminent or already existing overload via the control bus B~S to the out-side in order to request further paths for switching packets. For this, use can also be made, at least for some links, of paths set up by circuit switching.
However, buffers are also necessary, for example, if the start of a packet must first be determined from the contents of the incoming data stream and if, never-theless, the entire packet must be switched throughO
If packet switching is to be performed as described in the above-mentioned article by A~ Thomas et al with the aid of Fig. 9 of that artic~e, the subunits P1 .~. P4 must also contain the functional units for synchronization.
D.90ttle-H.Preisach-K.Schrodi 11 2-2 8~
In that case, in wh;ch the packets are so delayed that a broadband switching module 40 has to pro-cess the header of only a s;ngle packet at a time, the amount of c;rcuitry required in the handl;ng unit P and the decode and control logic 6 can be kept relatively small. It is suffic;ent, for example, if the address decoder PA is addressable from only one of the subunits P1 a~ P4 at a time~ Also, in the sec-ond packet-sw;tch;ng matrix PKZ, the decode and con-trol logic 6 never has to activate two crosspoints at a t;me. Even if the header of a packet contains address information for only one link and the address must be changed ;n the handling unit P, the amount of circuitry required in the necessary modules will be smaller if it is never necessary to process two headers at a time.
~n the embodiment, which shows a broadband switching module, i.e., a module operating at high speed, the combination of circuit switching and packet switching in accordance with the invention, unlike true circuit switching, requires that the crosspoints can be activat-ed quickly. At least part of the decode and control logic 6 must, therefore, be capable of operating at a speed apprGximately equal to the transmission speed.
For this reason, the decode and control logic 6 is di-v;ded into a slow portion 61 and a fast portior, 62~
The crosspoints in the first packet-switching matrix PK1 and in the switching matrix K are activated ~rom the slow portion 61, and those in the second packet-switching matrix PK2 from the fast por~ion 6Z~ The D.Bottle-H.Preisach-K.Schrodi 11-2 Z
8,V~
packet-handling unit P cooperates primarily with the fast portion 6Z.
In a digital switching network according to the inven-tion, the broadband switching modules described can be used as switching facilities. By some kind of central or decentralized control, paths for circuit-switched connections can be freely set up in a conventional manner. Alternatively, such paths can be preset for packet-switched messages. To this end, in each broad-band sw;tching module through which such a path is to lead, the ~irst packet-switching matrix PK1 must connect one of the subunits P1 ... P4 of the handling unit P to this path. In addition, the address decoder PA must be fed with the data required to properly route the packets subsequently to be switched on the path to be preset.
D~Battle-H.Preisach-K~Schrodi 11-Z-2 , .
Claims (8)
1. In a digital switching network having a plurality of inlets and outlets and a plurality of switching facilities each having a plurality of inputs and outputs through which possible paths for circuit-switched connection can be set up, each such possible path extending from a respective network inlet through at least one respective switching facility via an associated input and an associated output to a respective network outlet, with two of said possible paths for circuit-switched connections converging or diverging at a common said switching facility in which said two possible paths converge from a first pair of inputs of said common switching facility into a first single output of said common switching facility or in which said two possible paths diverge from a single input of said common switching facility into a pair of outputs of said common switching facility, the improvement comprising, packet-switching setup means for designating on demand both of said two possible paths for circuit-switched connections as two respective preset packet switched paths that are temporarily simultaneously available on demand for packet-switched messages each comprising one or more data packets identified with one or the other of said respective preset paths, and packet-switching means associated with at least said common switching facility for switching data packets identified with each of said two preset paths from the respective switching facility input associated with said each path to the respective switching facility output associated with said each path.
2. A combined circuit-switching and packet-switching facility comprising a plurality of input channels, a plurality of output channels, a switching matrix comprising a first set of crosspoint elements for connecting each output channel with every input channel, switching control logic responsive to external circuit-switched control signals for controlling the first set of crosspoint elements to thereby effect one or more relatively permanent circuit-switched connections between designated ones of said input channels and respective designated ones of said output channels, and a packet-handling unit comprising input selection means for connecting an input of the packet-handling unit to a selected one of the input channels, address decoder means for determining an associated one of said output channels from the information contained in a header of an input packet appearing at the selected input channel, and packet logic control means responsive to the address decoder means for causing the switching control logic to establish, for no longer than the duration of a single packet, a temporary packet-switched connection from the selected input channel to the output channel associated with said input packet.
3. A switching facility as claimed in claim 2, wherein said facility further comprises a second set of crosspoint elements;
said switching control logic is also coupled to said second set of crosspoint elements; the packet-handling unit has an output port which is selectively connectable to each of the output channels via said second set of crosspoint elements; said input packet passes through the packet-handling unit from said input to said output port, and the packet-handling unit further comprises processing means for processing said input packet before it appears at said output port.
said switching control logic is also coupled to said second set of crosspoint elements; the packet-handling unit has an output port which is selectively connectable to each of the output channels via said second set of crosspoint elements; said input packet passes through the packet-handling unit from said input to said output port, and the packet-handling unit further comprises processing means for processing said input packet before it appears at said output port.
4. A switching facility as claimed in claim 3, wherein said switching control logic further comprises a fast control logic for controlling the second set of crosspoint elements.
5. A switching facility as claimed in claim 4, wherein said fast control logic is faster than the portion of said switching control logic which controls said first switching matrix.
6. A switching facility as claimed in claim 3, wherein said processing means synchronizes said input packet before it appears at said output port.
7. A switching facility as claimed in claim 3, wherein said processing means temporarily stores said input packet before it appears at said output port.
8. A switching facility as claimed in claim 3, wherein said processing means alters the header information of said input packet before it appears at said output port.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP3702614.3 | 1987-01-29 | ||
| DE19873702614 DE3702614A1 (en) | 1987-01-29 | 1987-01-29 | DIGITAL COUPLING NETWORK FOR LINE AND PACKAGE SWITCHING AND COUPLING DEVICE TO THIS |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1282152C true CA1282152C (en) | 1991-03-26 |
Family
ID=6319779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000557553A Expired - Lifetime CA1282152C (en) | 1987-01-29 | 1988-01-28 | Digital circuit- and packet-switching network and switching facility therefor |
Country Status (11)
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| US (1) | US4903260A (en) |
| EP (1) | EP0276776B1 (en) |
| JP (1) | JPH0797776B2 (en) |
| KR (1) | KR960007583B1 (en) |
| CN (1) | CN88100334A (en) |
| AT (1) | ATE107826T1 (en) |
| AU (1) | AU601797B2 (en) |
| CA (1) | CA1282152C (en) |
| DE (2) | DE3702614A1 (en) |
| ES (1) | ES2058143T3 (en) |
| MX (1) | MX169074B (en) |
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| DE3504835A1 (en) * | 1985-02-13 | 1986-08-14 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | MONITORING CIRCUIT FOR DIGITAL SIGNALS |
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-
1987
- 1987-01-29 DE DE19873702614 patent/DE3702614A1/en not_active Withdrawn
-
1988
- 1988-01-18 AU AU10341/88A patent/AU601797B2/en not_active Ceased
- 1988-01-20 MX MX010153A patent/MX169074B/en unknown
- 1988-01-22 DE DE3850269T patent/DE3850269D1/en not_active Expired - Fee Related
- 1988-01-22 EP EP88100907A patent/EP0276776B1/en not_active Expired - Lifetime
- 1988-01-22 ES ES88100907T patent/ES2058143T3/en not_active Expired - Lifetime
- 1988-01-22 AT AT88100907T patent/ATE107826T1/en not_active IP Right Cessation
- 1988-01-27 JP JP1678388A patent/JPH0797776B2/en not_active Expired - Lifetime
- 1988-01-28 KR KR1019880000701A patent/KR960007583B1/en not_active IP Right Cessation
- 1988-01-28 CN CN88100334A patent/CN88100334A/en active Pending
- 1988-01-28 CA CA000557553A patent/CA1282152C/en not_active Expired - Lifetime
- 1988-01-28 US US07/149,664 patent/US4903260A/en not_active Expired - Lifetime
Also Published As
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|---|---|
| JPS63313938A (en) | 1988-12-22 |
| AU601797B2 (en) | 1990-09-20 |
| KR880009500A (en) | 1988-09-15 |
| EP0276776B1 (en) | 1994-06-22 |
| DE3702614A1 (en) | 1988-08-11 |
| AU1034188A (en) | 1988-08-04 |
| EP0276776A2 (en) | 1988-08-03 |
| KR960007583B1 (en) | 1996-06-05 |
| EP0276776A3 (en) | 1990-11-14 |
| ES2058143T3 (en) | 1994-11-01 |
| DE3850269D1 (en) | 1994-07-28 |
| US4903260A (en) | 1990-02-20 |
| JPH0797776B2 (en) | 1995-10-18 |
| CN88100334A (en) | 1988-09-21 |
| MX169074B (en) | 1993-06-21 |
| ATE107826T1 (en) | 1994-07-15 |
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